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Works on low-level software for AI accelerators, building and optimizing high-performance runtime systems focusing on scheduling, memory movement, and parallel execution. Core technologies include C/C++ and hardware/software boundary work.
Develop and optimize high-performance, low-level infrastructure (C/C++) for AI processors, working with Linux systems and debugging tools in a hybrid Toronto role.
Designs and implements RTL for high-performance RISC-V CPUs, collaborating with DV, PD, and performance teams to meet functional, timing, and power goals.
Design Verification Engineer for automotive robotics at Tenstorrent, building and executing verification plans for high-performance RISC-V CPUs and AI accelerators using SystemVerilog, UVM, and formal methods.
A Staff Engineer in Physical Design role at Tenstorrent, responsible for implementing high-performance blocks for CPU and AI/ML architectures, from synthesis to tapeout, optimizing performance, power, and area.
Implement physical design for RISC-V CPUs and AI architectures, owning the flow from synthesis to tapeout to optimize performance, power, and area.
Lead the definition and RTL implementation of datacenter-class System IP (MMUs, interconnects, memory controllers, peripherals) for Tenstorrent's next-generation AI/RISC-V SoCs. Hands-on technical leadership in Verilog/SystemVerilog with protocols like AXI, PCIe, DDR, and USB, based hybrid in Bangalore.
The Technical Program Manager drives end-to-end execution of next-generation SoCs from architecture through validation, requiring strong technical depth in silicon development and program management expertise. Core technologies include chip architecture, design flows, system-level tradeoffs, and project management tools like JIRA and Confluence.
Designs and implements high-performance AI and CPU System-on-Chip layouts, optimizing power, performance, and area while collaborating with architecture and packaging teams.
A Machine Learning Research Engineer working on LLM training, inference optimization, and large-scale distributed compute for Tenstorrent's custom AI accelerators, using Python, PyTorch, and techniques like speculative decoding and distributed training.
Software engineer writing low-level C/C++ kernels to optimize ML workloads on Tenstorrent's RISC-V AI hardware, tuning instruction-level performance for latency, memory, and bandwidth.
Design RTL for power management, interrupt controllers, and interconnects in RISC-V/ARM SoCs, optimizing for performance and power efficiency.
Leads end-to-end software development for a next-gen chiplet-based SiP in AI and CPU domains, spanning architecture, tape-out, silicon debug, and productization across pre- and post-silicon stages.
Maintain and troubleshoot cutting-edge AI hardware systems in R&D labs and data centers, supporting servers, PCIe devices, and prototype platforms for next-gen compute.
CPU Performance Modeling Architect at Tenstorrent building performance models to guide architectural decisions for next-generation RISC-V CPUs optimized for AI and HPC workloads, using tools like Gem5/SST and C++/Python.
Field Application Engineer who collaborates with sales and enterprise customers to drive adoption of AI/ML hardware-software solutions, bridging technical expertise with customer-facing communication.
Designs high-speed, multi-layer PCBs for AI CPUs, focusing on PCIe cards and server/desktop boards with tools like Allegro or Altium.
Build and operate CI/CD infrastructure and observability platforms for AI hardware and software development, diagnosing complex hardware/software issues.
Define next-gen chiplet-based CPU architectures for high-performance RISC-V systems, owning PCIe, die-to-die links, and system management while collaborating with hardware, software, and IP partners.
Build TT-Fabric, a low-level networking layer that ties thousands of RISC-V and AI processors into a single massively parallel supercomputer for AI workloads.
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