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Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Designs and implements high-performance AI SoC partitions from synthesis to tapeout, focusing on timing, power intent, and physical verification using Synopsys tools (Design Compiler, Fusion Compiler, IC Compiler II).
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Develop and optimize RISC-V AI/HPC software stacks and agentic systems using C/C++, working at the hardware-software boundary.
Develop high-performance Linux kernel and user-mode drivers for Tenstorrent's AI hardware, focusing on PCIe integration and cross-layer optimization.
Architect chiplets for next-generation AI automotive SoCs, translating requirements into specs that ensure performance, safety (ISO 26262), and scalability using RISC-V technology.
Software Engineer on the AI Models/System Bring-Up team responsible for porting, validating, and optimizing AI models on Tenstorrent platforms. Core technologies include PyTorch, TensorFlow, JAX, Python, C++, and Linux environments.
Works on low-level software for AI accelerators, building and optimizing high-performance runtime systems focusing on scheduling, memory movement, and parallel execution. Core technologies include C/C++ and hardware/software boundary work.
Develop and optimize high-performance, low-level infrastructure (C/C++) for AI processors, working with Linux systems and debugging tools in a hybrid Toronto role.
Designs and implements RTL for high-performance RISC-V CPUs, collaborating with DV, PD, and performance teams to meet functional, timing, and power goals.
Design Verification Engineer for automotive robotics at Tenstorrent, building and executing verification plans for high-performance RISC-V CPUs and AI accelerators using SystemVerilog, UVM, and formal methods.
A Staff Engineer in Physical Design role at Tenstorrent, responsible for implementing high-performance blocks for CPU and AI/ML architectures, from synthesis to tapeout, optimizing performance, power, and area.
Implement physical design for RISC-V CPUs and AI architectures, owning the flow from synthesis to tapeout to optimize performance, power, and area.
Lead the definition and RTL implementation of datacenter-class System IP (MMUs, interconnects, memory controllers, peripherals) for Tenstorrent's next-generation AI/RISC-V SoCs. Hands-on technical leadership in Verilog/SystemVerilog with protocols like AXI, PCIe, DDR, and USB, based hybrid in Bangalore.
The Technical Program Manager drives end-to-end execution of next-generation SoCs from architecture through validation, requiring strong technical depth in silicon development and program management expertise. Core technologies include chip architecture, design flows, system-level tradeoffs, and project management tools like JIRA and Confluence.
Designs and implements high-performance AI and CPU System-on-Chip layouts, optimizing power, performance, and area while collaborating with architecture and packaging teams.
A Machine Learning Research Engineer working on LLM training, inference optimization, and large-scale distributed compute for Tenstorrent's custom AI accelerators, using Python, PyTorch, and techniques like speculative decoding and distributed training.
Software engineer writing low-level C/C++ kernels to optimize ML workloads on Tenstorrent's RISC-V AI hardware, tuning instruction-level performance for latency, memory, and bandwidth.
Design RTL for power management, interrupt controllers, and interconnects in RISC-V/ARM SoCs, optimizing for performance and power efficiency.
Leads end-to-end software development for a next-gen chiplet-based SiP in AI and CPU domains, spanning architecture, tape-out, silicon debug, and productization across pre- and post-silicon stages.
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