Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Solutions Architect (Pre-Sales) advises Fortune 500 clients on Workato’s AI-powered integration platform, mapping technical capabilities to business outcomes across IT, HR, Finance, and RevOps. Focuses on iPaaS, agentic automation, and cloud ecosystems to drive enterprise adoption.
The Senior Golang Engineer will design and build scalable backend services, distributed systems, and API infrastructure for Workato's automation platform. The role involves working with Go, microservices, and cloud-native technologies to maintain high-performance connectors and system stability.
The Associate Creative Designer will support the APJ marketing team for a 3-month contract by creating digital and print assets, including landing pages, social graphics, and event materials. The role requires proficiency in Adobe Creative Suite, Figma, and motion graphics tools to deliver high-quality visual content.
Develop and validate software diagnostics for hardware blocks in AMD's System-on-chips, focusing on power management, using C/C++ and Python in Singapore.
Bridges client requirements and delivery, driving design intent and optimizing cooling solutions for large-scale data center facilities. Leads workshops, reviews designs, and coordinates teams for energy-efficient infrastructure across EMEA.
GCP Cloud DevOps Architect responsible for leading large-scale cloud migrations from on-premises to Google Cloud Platform, designing automation frameworks, CI/CD pipelines, and implementing infrastructure as code using Terraform and containerization with Docker/Kubernetes.
Senior DevOps role focusing on Ansible and network automation to modernize infrastructure. Daily tasks include automating deployments, managing large-scale networks, and contributing to CI/CD pipelines in an Agile environment.
Account Development Representative at MongoDB identifies and qualifies new sales opportunities, nurtures leads, and sets introductory meetings for the sales team using Salesforce and strong communication skills.
Designs and optimizes production-grade Kubernetes clusters for global enterprises, focusing on hybrid/multi-cloud data workloads and storage solutions. Advises customers and engineering teams on cloud-native architectures, automation, and high-availability data platforms.
Maintains and scales enterprise server infrastructure, virtualization (VMware), Windows Server environments, and automation (PowerShell/Ansible) for a remote-first team.
Principal engineer on Microsoft’s Azure Kubernetes Service team, building and improving cloud-native container orchestration and DevOps tools for Azure.
Lead a team to verify system-on-chip designs for memory/storage solutions, ensuring first-pass silicon success and collaborating with architecture and validation teams.
Lead analog design for high-speed Serdes transceivers, defining circuits and supervising teams to deliver silicon-validated IP for interfaces like PCIe and UCIe using advanced CMOS processes.
Develops firmware for next-gen memory solutions like HBM, working with ARM cores, RTOS, and hardware bring-up while collaborating with cross-functional teams.
Design low-power analog and mixed-signal Serdes circuits (USB, PCIe, UCIe) for high-speed interconnects using advanced CMOS processes and validate them in silicon.
Design high-speed I/O interfaces for Samsung’s AI SoCs, focusing on chiplet die-to-die links and PHY IP while collaborating with analog and system teams.
Senior Staff Engineer leads the design and optimization of EDA (Electronic Design Automation) environments and large-scale compute infrastructure for Samsung Semiconductor’s semiconductor design teams, ensuring productivity and cost efficiency through standardization, vendor management, and infrastructure roadmapping.
Build and deploy agentic AI systems for semiconductor design workflows, optimizing LLM inference and multi-agent orchestration on large-scale compute infrastructure.
Senior Physical Design Engineer responsible for physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, and routing. Core technologies include EDA tools like Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC, with expertise in timing closure, low-power design, and s
Design and verify next-gen ASICs using SystemVerilog/UVM, collaborating with architects and engineers to ensure first-pass silicon success.
We couldn't check your fit for this role — add a CV to your profile to see it next time.