A senior NPU architect at Samsung's SoC Architecture Lab who defines next-generation NPU subsystem architectures for Galaxy chipsets, doing early-stage architectural exploration, cycle-accurate performance/power modeling, and hardware-software co-optimization. Core work spans Python/C++/SystemC modeling, ML workloads (CNNs, LLMs via TensorFlow/PyTorch/ONNX), and SoC microarchitecture.
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