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Leads a team validating cutting-edge AI connectivity silicon and systems for Astera Labs, ensuring performance and reliability for hyperscale AI deployments using CXL, PCIe, Ethernet, and related protocols.
Senior engineer validates high-speed connectivity chips and boards for AI data centers, designing automated tests for CXL, PCIe, and Ethernet compliance and performance.
Senior engineer validates AI connectivity SoCs on emulation platforms, debugging high-speed interfaces like PCIe and Ethernet before silicon tape-out.
Designs and implements advanced semiconductor packages for high-performance AI connectivity chips, collaborating with teams to optimize electrical, thermal, and mechanical performance from concept to production.
Leads validation of AI connectivity chips and boards, designing tests to verify performance and compliance with high-speed interfaces like PCIe and Ethernet.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads validation and characterization of advanced photonic integrated circuits (PICs) integrated with electronic ICs for high-speed data center and AI applications, using optical and electrical testing tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Designs and runs tests to validate high-speed semiconductor chips (CXL, PCIe, Ethernet) for AI infrastructure, ensuring reliability and performance in server/storage systems.
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