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Design Verification Engineer verifying Velaura's next-generation Physical AI SoC in Bangalore: building UVM/SystemVerilog and C++ verification environments, running formal verification, emulation, and FPGA prototyping, and performing HW/SW co-verification and debug from RTL blocks through post-silicon.
The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with…
Senior engineer doing RTL and FPGA design and verification of digital blocks for Omni Design's next-generation wireless chips targeting automotive and space applications. Day to day: analyzing power/performance/area tradeoffs, implementing test strategy and BIST, validating on FPGA, and leading silicon design with Verilog/SystemVerilog, UVM, C/C++ and scripting.
Leads and manages the digital engineering team at Omni Design Technologies, driving development of mixed-signal SoCs for automotive and space applications — from RTL design, integration, and verification through timing closure and silicon validation. Core tools: Verilog/SystemVerilog, UVM, Cadence/Synopsys flows, and FPGA emulation.
Pre-silicon GPU verification engineer at Intel: builds and executes IP-level verification plans, SystemVerilog/UVM test benches, and simulations for 3D graphics, media, and display logic; debugs failing tests and collaborates with GPU architects, RTL, and physical design teams. Hybrid work model at US Intel sites.
Designs and integrates microarchitecture, RTL logic, and verification environments across multiple IPs for Intel's client chipsets and SoC products, including pre-silicon validation, test plans, and debugging. Core focus on RTL design, UVM, and formal verification; on-site role in Penang, Malaysia.
Entry Level - Electrical Engineering, Computer Engineering, or related field. Bachelor's degree with up to 2 years of experience or recent master's grad with no experience. Duluth, GA - HYBRID Renesas is…
GPU Design Verification Engineer on AMD's verification team in Markham, Ontario, driving functional and performance closure on digital design blocks of the Graphics Core IP (GFXIP) using UVM, SystemVerilog, Verilog and C/C++, including AI-driven verification automation. Requires a bachelor's or master's in computer/electrical engineering; visa sponsorship is not available.
Design verification engineer at Cerebras Systems, defining verification strategies and building SystemVerilog/UVM testbenches, coverage plans and regression infrastructure for its wafer-scale AI chip, and debugging across simulation, emulation, and silicon bring-up. On-site in Sunnyvale, CA; requires 14+ years of DV experience. Pays $250k-$300k base.
Design Verification Engineer who builds verification strategies, UVM/SystemVerilog testbenches, and coverage plans for Cerebras' wafer-scale AI chips, running regressions and debugging across simulation, emulation, and silicon bring-up. Requires 3+ years of DV experience plus Python/Perl scripting; onsite in Sunnyvale, CA.
Staff-level individual contributor at SiFive verifying L2/L3 cache and memory-subsystem functionality — cache coherency, ordering, and correctness — from block level through subsystem integration. Day-to-day involves building SystemVerilog/UVM testbenches, assertions, checkers, and coverage models, plus debugging issues across RTL and testbench layers.
Senior Design Verification Infrastructure Engineer at SiFive (Bengaluru) who architects and maintains the company's Chisel/Scala-based Verification Platform: building reusable testbench components, VIPs/AIPs, stimulus, scoreboards, and test plans with SystemVerilog and UVM, and educating DV teams on best practices.
Senior Customer Release Engineer at SiFive (RISC-V chip IP) in Bengaluru: owns release readiness and on-time delivery of IP customer drops, integrating and validating Core/UnCore content, generating release collateral, and coordinating across engineering, PMs, and sales. Core stack: Python, JSON/YAML/IP-XACT, C/C++/Assembly with CMake/Make, Linux, Git, Jira.
Program Manager leading the end-to-end lifecycle of automotive networking chip (ASIC/SoC) development at Ethernovia — planning schedules, budgets, and cross-functional execution from concept to silicon, while ensuring ISO 26262, ISO/SAE 21434, and ASPICE compliance and managing key customer relationships.
Technical lead/manager for AMD's Security IP team in Ottawa, running the team that does hardware/firmware co-verification of embedded processor subsystems and SoC accelerators (cryptography, compression, DMA) using UVM SystemVerilog, C-DPI testbenches, and FPGA prototypes, plus hiring, mentoring, and performance management.
Senior Design Verification Engineer on Microsoft's custom silicon team (Azure Cobalt), verifying custom IP at block and sub-system level across pre-silicon (UVM simulation, emulation, FPGA) and post-silicon validation. Core stack: UVM, C/C++ testbenches, silicon bring-up, coverage closure, and formal verification with Jasper.
Leads design verification for Google's custom silicon (SoC) teams in Bengaluru: managing engineers, driving pre-silicon emulation (Palladium/Zebu/SimXL), post-silicon debug, and verification methodology built on UVM, SystemVerilog, and scripting in Python/Perl.
Dein Team OMR Education ist die erste Adresse für lebenslanges Lernen im digitalen Marketing. Wir helfen Unternehmen und Professionals dabei, in einer sich ständig wandelnden Digitalwirtschaft nicht nur Schritt zu…
Wir sind Evernest – das Immobilienunternehmen, das Technologie und persönliche Beratung auf höchstem Niveau vereint. Mit digitalen Tools, maßgeschneiderten Marketingstrategien und tiefem lokalen Marktverständnis machen…
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