Tech jobs

Analog and Mixed Signal Design Engineer

Open 59d North America

Cadence Virtuoso Perl Python Verilog

Broadcom is seeking an experienced Analog and Mixed-Signal Design Engineer to design and verify on-die PVT monitoring IP. The role involves circuit design, layout validation, digital modeling, and silicon bring-up using tools like Cadence Virtuoso and Synopsys PrimeTime.

110K – 176K $

Synopsys

ADAS AI Automation Iso 26262 Iso 9001 +5 skills

ASIC Digital Design, Staff Engineer - 18421

Open 53d Staff

Staff FuSa Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation…

Qualcomm

Open 41d On-siteAPACStaff H-1B sponsor history

WRD(RTL ) Design - Staff/Manager

Automation FPGA Oscilloscope Perl REST Assured +5 skills

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: BDC WRD (Wi-Fi) is responsible for developing Qualcomm’s Wi-Fi chips. We are looking for a…

Qualcomm

Open 32d On-siteAPACLead H-1B sponsor history

SOC Design - Sr Lead

Asic PCIe REST Assured Rtl Verilog

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 8 to 11 years of work experience in ASIC/SoC Design Experience in Logic design…

Code Metal

Open 95d HybridNorth AmericaMiddle

Forward Deployed Engineer

AI Candidate Experience Computer Vision C++ CUDA +10 skills

Forward Deployed Engineer owning end-to-end deployment of DSP, RF, and communications algorithms onto GPUs, FPGAs, ASICs, and edge SoCs, working directly with defense and aerospace customer teams in mission-critical environments.

Code Metal

Open 95d HybridNorth AmericaMiddle

Solutions Architect

AI Candidate Experience C++ CUDA MATLAB +7 skills

Solutions Architect leading technical discovery with defense, automotive, and aerospace customers to define system architectures and proofs of concept for translating algorithms onto GPUs, FPGAs, ASICs, and edge SoCs.

Code Metal

Open 61d HybridNorth AmericaMiddle

Solutions Engineer

AI Candidate Experience Computer Vision C++ CUDA +10 skills

Solutions Engineer building proofs of concept and validating customer solutions on Code Metal's code translation platform, targeting GPUs, FPGAs, ASICs, and edge SoCs for defense, aerospace, and automotive partners.

SopraSteria1

Open 61d HybridNorth AmericaMiddle Licensed UK sponsor Licensed NL sponsor

FPGA Development Engineer (Mid level)

Embedded Systems FPGA Python SystemVerilog Verilog +1 skills

FPGA Development Engineer designing and implementing safety-critical airborne systems using VHDL, Verilog/SystemVerilog, and Python, ensuring DO-254 compliance for aerospace and defense projects.

SopraSteria1

Open 61d HybridNorth AmericaSenior Licensed UK sponsor Licensed NL sponsor

FPGA Development Engineer (senior level)

Embedded Systems FPGA Python SystemVerilog Verilog +1 skills

This senior FPGA Development Engineer role involves leading the design and development of safety-critical airborne systems in accordance with DO-254 standards. The position requires expertise in VHDL, Verilog, and embedded hardware architectures to guide technical implementation and mentor junior staff.

Microsoft

Open 89d On-siteNorth AmericaFull-timePrincipal

Principal AI Silicon Architect

AI Azure Cloud C++ Firmware +4 skills

Principal AI Silicon Architect designs and optimizes hardware architectures for AI workloads, collaborating with software and hardware teams to deliver high-performance, scalable cloud infrastructure at Microsoft.

143K – 275K $

Apple

Open 61d UKInternshipIntern

GPU Design Verification Internship

United Kingdom

This internship role involves working on GPU design verification, emulation, and driver development for Apple Silicon SoCs. Interns will contribute to verification plans, testbench development, and emulation infrastructure using C/C++, scripting languages, and hardware description languages.

C++ Design Patterns Express.js GPU Perl +6 skills

Apple

Open 61d UKInternshipIntern

GPU Internships - RTL Design, RTL Power Optimisation & Physical Design

United Kingdom

Apple is offering GPU internships in the UK focused on RTL design, power optimization, and physical design for Apple Silicon. Interns will collaborate with engineering teams on chip architecture, power analysis, and ASIC design flows using languages like C++, Python, and Verilog.

Asic C++ Express.js GPU Perl +7 skills

Ceva, Inc.

Bluetooth Embedded Systems FPGA IoT Prototyping +2 skills

Digital Design Engineer

Open 53d Hybrid

About the Business Unit: Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer. Within the Wireless…

Advanced Micro Devices, Inc

Senior Lead Verification Engineer

Open 130d APACLead

AI Asic Embedded Systems Perl Rtl +3 skills

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…

NXP Semiconductors

Open 62d APACSenior Licensed NL sponsor

SENIOR DESIGN ENGR

Assembly IoT SystemVerilog Uvm Verilog

The Senior Design Engineer will design and verify high-performance RISC-V CPU cores for automotive and IoT SoCs. The role focuses on microarchitecture development, RTL coding, PPA optimization, and comprehensive functional verification.

Analog Devices

Open 62d North AmericaInternshipIntern Licensed UK sponsor H-1B sponsor history

Digital Design Engineer Intern

AI Automation FPGA Prototyping Rtl +2 skills

This internship role involves assisting with the design, simulation, and verification of digital integrated circuits using Verilog or VHDL. Interns will work on FPGA prototyping, digital modeling, and timing analysis alongside experienced engineers.

19 – 35 $ / hr

Syntiant

Open 61d APACStaff H-1B sponsor history

Senior Staff Digital Design Engineer - Audio DSP Algorithm

AI Asic C++ Deep Learning MATLAB +6 skills

The Senior Staff Digital Design Engineer will lead the design, implementation, and verification of DSP algorithms and digital control logic for audio processing within ASIC systems. This role involves the full ASIC design flow, from specification to silicon bring-up, utilizing expertise in digital signal processing and mixed-signal integrated circuits.

RTX

Open 61d On-siteNorth AmericaSenior

Senior Electrical Engineer - FPGA (Onsite)

Agile Asic Ethernet FPGA Git +6 skills

Designs and develops FPGA-based digital solutions for aerospace/defense systems, including RTL architecture, verification, timing closure, and system integration. Works in Agile teams, mentors junior engineers, and collaborates on mission-critical hardware projects requiring security clearance.

87K – 165K $

ARM