Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and implement Verilog RTL for SoC blocks, integrate IPs, and optimize performance through synthesis, timing closure, and power reduction in a semiconductor R&D team.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Job Overview: This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the…
Designs and implements high-performance RISC-V CPU and SoC RTL modules using SystemVerilog, collaborating with architects, verification, and backend teams to optimize performance, power, and area.
Position Description This role will be part of the Global Market Connectivity team responsible for supporting Exchange Connectivity systems for various exchanges and servicing Market Data applications. Working closely…
Lead validation of Cadence’s Innovus EDA tool, focusing on place-and-route features, writing Perl/Tcl/Python test utilities, and improving regression coverage.
Maintains and secures Linux servers and infrastructure, writes automation scripts, and troubleshoots issues in a classified environment for a government contractor.
Job Description Meet the Team Join the Package Design Team at Cisco Silicon One in Armenia, a group leading the way in developing Cisco's groundbreaking silicon solutions for next-generation networking. As a…
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Design and validate power delivery systems for next-gen networking hardware, selecting components, debugging boards, and ensuring robust performance in HPE’s R&D team.
Senior Linux engineer maintaining and optimizing cloud hosting infrastructure, troubleshooting complex server issues, and automating deployments with KVM, Ansible, and Python.
Join Euronext as a SNOC Engineer Support To deliver level 1/2 technical support for the infrastructures of multiple entities, ensuring the continuity and reliability of Euronext’s business operations. The disciplines…
Designs and verifies mixed-signal SoCs for wireless systems, building analog/system models and testbenches in SystemVerilog/VerilogAMS to validate functionality before tape-out.
Principal Digital Design Engineer designing secure embedded controllers and cryptographic hardware for automotive, industrial, and defense markets using ASIC/FPGA flows, Verilog/VHDL, and security countermeasures.
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique…
Type of Requisition: Regular Clearance Level Must Currently Possess: None Clearance Level Must Be Able to Obtain: None Public Trust/Other Required: None Job Family: IT Infrastructure and Operations Job Qualifications:…
Designs and optimizes advanced ASICs for Cisco’s networking hardware, using EDA tools like Innovus and Tempus to perform RTL-to-GDSII flows, timing closure, and power integrity analysis.
Design and validate power delivery systems for next-gen networking hardware, from schematics to board bring-up and testing using Cadence tools and scripting.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
