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Designs and maintains Julius Baer’s global financial messaging infrastructure using IBM MQ, IBM App Connect Enterprise, and IBM MQ MFT to securely exchange critical data across systems.
Designs and validates next-generation GPU and SoC architectures using SystemC/TLM, C++, and build tools to model graphics and parallel-compute features for high-performance computing.
Designs and leads the development of high-performance microcontrollers for edge AI applications, using Verilog/SystemVerilog, synthesis, and verification tools.
ASX: Powering Australia's financial markets Why join the ASX? When you join ASX, you’re joining a company with a strong purpose – to power a stronger economic future by enabling a fair and dynamic marketplace for…
Designs and validates high-performance ASIC chips for Cisco's networking solutions using Verilog/SystemVerilog, CDC, lint, and formal verification, from architecture through tape-out and lab validation.
Our vision for the future is based on the idea that transforming financial lives starts by giving our people the freedom to transform their own. We have a flexible work environment, and fluid career paths. We not only…
OTC Markets Group Inc. Associate, Financial Application Support Specialist OTC Markets Group - India - Full Time OTC Markets Group Inc., operator of premier US financial marketplaces, is the largest stock market in the…
Leads software configuration management for defense systems using IBM Rational ClearCase, ensuring controlled, auditable builds and releases while collaborating with cross-functional teams in a classified environment.
Senior Oracle DBA and system administrator maintaining Oracle E-Business Suite R12 databases on Exadata hardware, ensuring performance, security, and high availability for a global security company.
A Secure Configuration Systems Engineer at State Street who implements secure configuration best practices, system hardening, and develops solutions using tools like Ansible and Chef Inspec to secure the company’s digital footprint.
Maintains Redhat Linux and Windows Server systems for a government contract, including cloud environments, VMware, and SAN/NAS storage while ensuring compliance with SLAs and security standards.
Own silicon speed characterization for NVIDIA’s AI chips, bridging pre-silicon models and real hardware to validate frequency, voltage margins, and timing across PVT corners.
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Lead validation of next-gen DRAM memory chips, defining specs, running circuit simulations, and debugging failures to ensure product quality from design through manufacturing.
Principal engineer verifying advanced modem PHY IP for Blue Origin’s Terawave satellite network, ensuring high-speed wireless ASIC designs meet performance and integration requirements.
Develop real-time software in C++ to control missile flight simulators, integrating hardware and software for defense systems testing.
Engineer II Systems (HPC) Location: India - Chennai Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the…
Physical Design Expert We’re looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, responsible for developing both Technology Methodologies & Flows for all products…
Senior FPGA Engineer- ASIC/FPGA, Mission Systems (Hybrid) Location: US-PR-AGUADILLA-110 ~ Rd 110 N Km 28.8 ~ RD110 Time Type: Full time Job Description Date Posted: 2026-07-23 Country: United States of America…
Electrical Engineer II- ASIC/FPGA (Onsite) Location: US-MD-ABERDEEN-APG ~ 6260 Guardian Gtwy ~ APG Time Type: Full time Job Description Date Posted: 2026-07-24 Country: United States of America Location:…
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