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Senior Product Manager at Crusoe to lead Kubernetes-based orchestration for AI infrastructure, defining product roadmaps and collaborating with engineering to deliver scalable, reliable systems for AI workloads.
Qumulo's cloud data platform manages exabytes of the world's most demanding data, unifying files, objects, and every workload across edge, core, and cloud. About the Senior Pre-Sales Systems Engineer role As…
Leads global teams to deliver high-performance computing SoC and MCU chips from RTL to GDS, ensuring PPA targets and on-time tape-outs while scaling engineering practices across sites.
Builds and maintains the Linux host software stack for OpenAI's large GPU clusters, including OS images, kernels, drivers, and provisioning systems to ensure reliable AI model training.
Designs and optimizes GPU servers and rack-scale systems for an AI infrastructure platform, collaborating with vendors and ODMs to maximize performance, reliability, and cost efficiency.
Designs and builds the networking backbone for a next-gen AI cloud platform, focusing on multi-tenant isolation, high-performance connectivity, and automation across vendors like Arista and Juniper.
Designs and validates liquid cooling systems for high-performance AI and data center GPUs, using thermal simulations and lab testing to optimize cooling solutions.
Lead the physical design of next-generation AI chips in London, optimizing performance, power, and area using EDA tools like Cadence Innovus and Synopsys Fusion Compiler.
Leads the physical design of next-generation AI chips in Bristol, optimizing performance, power, and area using EDA tools like Cadence Innovus and Synopsys Fusion Compiler.
Build and deploy GenAI solutions like RAG systems and AI agents in Python, integrating them into cloud environments and enterprise systems while advising clients on value, security, and scalability.
Designs and maintains AWS-based cloud and Linux infrastructure for semiconductor design workloads, focusing on HPC, automation, and security in a deep-tech startup environment.
Senior Physical Design Engineer at Bitdeer in Singapore designs and implements high-speed PCIe IP for AI chips, owning the full physical design flow from netlist to GDSII using advanced EDA tools.
Designs, maintains, and troubleshoots high-performance InfiniBand and Ethernet networks for HPC/AI workloads, using Fortinet security tools and Linux systems.
Designs and integrates RISC-V CPU cores with custom extensions for ASIC chips in Bitcoin mining and AI cloud hardware, using Verilog/SystemVerilog and collaborating with cross-functional teams.
Lead a team to design and operate a massive GPU fleet for AI workloads, ensuring high availability and automation while scaling to nation-level power usage.
Design Verification Engineer at Bitdeer in Singapore who builds and runs test environments for ASIC chips and AI cloud hardware using UVM, SystemVerilog, and formal tools to ensure functional correctness before silicon.
Designs and implements RTL (Verilog HDL) for ASIC chips, including microarchitecture, IP integration, and collaboration with verification/implementation teams for tape-out.
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