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Designs and executes verification environments for custom silicon (ASICs/TPUs) at Google Cloud, focusing on constrained-random testing, coverage closure, and debugging digital designs with SystemVerilog/UVM. Core tech: SystemVerilog, UVM, SVA, ASIC verification.
The Semiconductor Software Engineer designs and builds software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation workflows. The role involves working with C, C++, and Python to optimize compute-intensive processes and data pipelines for silicon characterization.
Wir sind mehr als eine Bank: Als Partner im genossenschaftlichen Verbund begleiten wir das Wachstum der EDEKA-Kaufleute in ganz Deutschland. Mit Leidenschaft setzen wir uns dafür ein, dass über 400.000 Edekaner\*innen…
The Senior Custom Logic Engineer will lead the design, simulation, and certification of FPGA, ASIC, and CPLD devices for avionics hardware applications. The role involves managing project lifecycles, developing technical requirements, and utilizing VHDL to create complex hardware solutions.
Wright Canada Holdings, Ltd. Job Summary: The Senior Manager, Safety and Risk Compliance will provide support to Wright Canada Holdings. This role will assist in evaluating and implementing Environment, Health and…
Design and execute UVM-based verification plans for Intel SoCs, debugging presilicon issues and collaborating with RTL and architecture teams to ensure functional correctness.
System Test Engineer verifying next-generation AI/ML neural network hardware accelerators at Arm, designing test automation and working with emulation platforms (ZeBu/Palladium/Strato) and RTL (SystemVerilog).
The System Architect Verification Engineer develops behavioral models and testbenches in System Verilog and RTL to validate optical engine control algorithms and hardware bring-up sequences before silicon production. This role involves close collaboration with ASIC and firmware teams to ensure system accuracy through pre-silicon simulation and regression testing.
Senior Network Engineer responsible for high-level design (IPv4/IPv6), troubleshooting, and management of UVM's wired and wireless network infrastructure across academic, research, administrative, and residential environments.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
The Senior Java Developer will design and develop complex applications while mentoring agile teams and contributing to architecture and service optimization. The role requires deep expertise in Java, modern development tools like Docker and Jenkins, and strong communication skills in German.
Senior Backend Developer building scalable backend systems for industry clients (e.g., automotive process automation) using .NET, Java, or Node.js ecosystems in an agile, self-organized project team.
Design Verification Engineer at Bitdeer in Singapore, responsible for verifying complex digital ASIC designs using UVM, SystemVerilog, and industry tools to ensure functional correctness and silicon quality.
Leads a team to verify complex ASIC/SoC designs for Bitcoin mining and AI cloud hardware, using UVM, SystemVerilog, and protocol knowledge (AXI, NoC, RISC-V) to ensure silicon quality.
Design and deploy ML models directly onto custom hardware, co-architecting solutions with traders and engineers while optimizing for latency and resource constraints.
This graduate role involves working with verification experts to verify DDR subsystems using SystemVerilog, UVM, and formal verification techniques. The engineer will write tests, develop testbench components, and track verification quality metrics like code and functional coverage.
Lead functional verification for complex IP blocks and SoC designs using System Verilog and UVM frameworks, focusing on NAND flash memory verification at Sandisk.
Senior Staff VLSI Design Engineer coding C++ and SystemC functional models and testbenches for memory/storage products, validating models using SystemC/SV/UVM, debugging firmware issues, and mentoring junior engineers.
Lead VLSI design verification for complex IP blocks and SoC designs using UVM, SystemVerilog, and formal verification tools like Xcellium, Verdi, and JasperGold.
Principal Digital Design Engineer owning the architecture and RTL development of a configurable IO subsystem for onsemi's microcontroller platform, using SystemVerilog, Python-based design generators, and UVM verification in Allen, TX.
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