Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
Build and improve Rust-based compilers, runtimes, and low-level GPU systems for AMD, focusing on correctness, safety, and performance across the GPU software stack.
Design Verification Engineer at AMD building and running testbenches for DDR5/LPDDR5 memory interfaces using SystemVerilog, UVM, and C/C++ to validate server memory products.
Designs and implements high-performance GPU/SoC physical layouts using EDA tools, timing closure, and signoff to meet power/area/schedule targets.
Lead a team designing and integrating RTL for SoC subsystems, ensuring first-pass silicon success through collaboration with architecture, verification, and physical design teams.
Designs and implements physical layouts for high-performance chip IP, owning floorplanning through GDS tape-out on advanced nodes (28nm or below).
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
SMTS Logic Design Location: Montreal, UNAVAILABLE, CA Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of…
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
Lead MTS Applications Engineering Location: San Jose, CA, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Application Engineer to join our…
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
Own the 0-to-1 launch of a kids and family financial-empowerment product, partnering with credit unions to build safe, engaging savings and literacy features while navigating compliance for minors.
Security Analyst develops and maintains cyber defense methods, analyzes threats, and uses tools like Tenable and McAfee HBSS to detect and report malicious activity for the U.S. Army.
Develops cyber defense tools for the U.S. Army, using Python, JavaScript, and cloud/virtualization tech to build and maintain systems like Interrogator and CSSP Subscriber Manager.
Design and implement cloud-native solutions on GCP/AWS, set solution intent, and oversee implementation while ensuring alignment with enterprise standards and non-functional requirements.
Lead RMF and security operations for DoD systems in Azure and DISA environments, hardening Kubernetes, RHEL, and web stacks against threats.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
