Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
About Elveo Elveo is what happens when two pioneers in direct-to-device (D2D) communications join forces. Elveo brings together a combined 20 years of expertise to close the coverage gap for more than 50 mobile network…
Lead functional verification of PCIe/CXL semiconductor connectivity designs—develop UVM test plans, write assertions and coverage, debug with RTL designers, and build VIP abstraction layers for SoC products.
Junior AI SoC Design Verification Engineer at Google, planning and executing verification of custom silicon using SystemVerilog, UVM, and formal methods throughout the full development lifecycle to tape-out.
Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power…
Du wirst Teil unseres ambitionierten Sales & Partnerships Teams bei OMR . Mit uns gemeinsam betreust du die spannendsten nationalen und internationalen Partner*innen aus dem Digital- und Brandbereich. Dabei machen…
The Software Developer will design, develop, and maintain Warehouse Management System (WMS) solutions using Java and Spring Boot. The role involves refactoring code, performing system tests, and collaborating with cross-functional teams to optimize logistics software.
Designs and executes verification environments for custom silicon (ASICs/TPUs) at Google Cloud, focusing on constrained-random testing, coverage closure, and debugging digital designs with SystemVerilog/UVM. Core tech: SystemVerilog, UVM, SVA, ASIC verification.
The Semiconductor Software Engineer designs and builds software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation workflows. The role involves working with C, C++, and Python to optimize compute-intensive processes and data pipelines for silicon characterization.
Wir sind mehr als eine Bank: Als Partner im genossenschaftlichen Verbund begleiten wir das Wachstum der EDEKA-Kaufleute in ganz Deutschland. Mit Leidenschaft setzen wir uns dafür ein, dass über 400.000 Edekaner\*innen…
The Senior Custom Logic Engineer will lead the design, simulation, and certification of FPGA, ASIC, and CPLD devices for avionics hardware applications. The role involves managing project lifecycles, developing technical requirements, and utilizing VHDL to create complex hardware solutions.
Design and execute UVM-based verification plans for Intel SoCs, debugging presilicon issues and collaborating with RTL and architecture teams to ensure functional correctness.
System Test Engineer verifying next-generation AI/ML neural network hardware accelerators at Arm, designing test automation and working with emulation platforms (ZeBu/Palladium/Strato) and RTL (SystemVerilog).
The System Architect Verification Engineer develops behavioral models and testbenches in System Verilog and RTL to validate optical engine control algorithms and hardware bring-up sequences before silicon production. This role involves close collaboration with ASIC and firmware teams to ensure system accuracy through pre-silicon simulation and regression testing.
Senior Network Engineer responsible for high-level design (IPv4/IPv6), troubleshooting, and management of UVM's wired and wireless network infrastructure across academic, research, administrative, and residential environments.
The Senior Java Developer will design and develop complex applications while mentoring agile teams and contributing to architecture and service optimization. The role requires deep expertise in Java, modern development tools like Docker and Jenkins, and strong communication skills in German.
Senior Backend Developer building scalable backend systems for industry clients (e.g., automotive process automation) using .NET, Java, or Node.js ecosystems in an agile, self-organized project team.
Design Verification Engineer at Bitdeer in Singapore, responsible for verifying complex digital ASIC designs using UVM, SystemVerilog, and industry tools to ensure functional correctness and silicon quality.
Design and deploy ML models directly onto custom hardware, co-architecting solutions with traders and engineers while optimizing for latency and resource constraints.
This graduate role involves working with verification experts to verify DDR subsystems using SystemVerilog, UVM, and formal verification techniques. The engineer will write tests, develop testbench components, and track verification quality metrics like code and functional coverage.
Lead functional verification for complex IP blocks and SoC designs using System Verilog and UVM frameworks, focusing on NAND flash memory verification at Sandisk.
We couldn't check your fit for this role — add a CV to your profile to see it next time.