Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Title: Data Center Technician II Workplace Type: On-site Location: Data Center Environment Role Overview This is a long-term opportunity supporting the build-out, deployment, and ongoing operations of an NVIDIA Data…
Principal Field Applications Engineer at Astera Labs designs and supports AI infrastructure connectivity solutions for cloud providers and OEMs using CXL, Ethernet, PCIe, and related technologies.
Leads a Shanghai hardware design team to develop high-speed Active Electrical Cables and Smart Cable Modules for AI infrastructure, while providing local customer engineering support to China-based hyperscalers and OEMs.
Lead a new Taiwan hardware engineering hub to design validation platforms and rack-scale systems for AI connectivity, while partnering with OEMs across Asia to integrate Astera Labs’ silicon into their products.
Lead a hardware engineering team at a NASDAQ-listed AI connectivity company, designing high-speed cables, modules, and rack-scale systems while enabling OEM customers to integrate Astera Labs' silicon into their products.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Principal Field Applications Engineer designs and supports AI connectivity solutions for cloud providers and OEMs, focusing on PCIe, Ethernet, and CXL technologies.
Designs power delivery systems and PCB layouts for ASIC-based AI connectivity hardware, using Cadence OrCAD/Allegro and collaborating with cross-functional teams.
Principal firmware engineer at Astera Labs, building and debugging C/Python code for CXL and DDR memory subsystems while acting as the technical liaison for hyperscale customers and OEMs.
Principal Product Application Engineer at Astera Labs designs and troubleshoots PCIe connectivity solutions for AI infrastructure, working with hyperscalers and OEMs to deploy high-speed retimers and influence product direction.
Quality Engineer driving root-cause analysis of failures across semiconductor circuit, package, firmware, and protocol layers for PCIe and Ethernet connectivity solutions. Uses advanced lab instrumentation (BERT, oscilloscopes, VNAs, TDR) to debug high-speed SERDES and collaborates cross-functionally to ensure product reliability for AI infrastructure hardware.
Leads a team validating cutting-edge AI connectivity silicon and systems for Astera Labs, ensuring performance and reliability for hyperscale AI deployments using CXL, PCIe, Ethernet, and related protocols.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Leads the product strategy for a unified management suite that orchestrates software, firmware, and silicon across Astera Labs' AI connectivity products, focusing on PCIe, CXL, and Ethernet technologies.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
We couldn't check your fit for this role — add a CV to your profile to see it next time.