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Engineer firmware for CXL Smart Memory Controllers, debugging and validating memory subsystems on customer platforms using C and Python, and providing technical guidance to hyperscalers and OEMs.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Lead embedded firmware development for analog and Ethernet connectivity devices, writing C/C++ code for calibration, link management, and hardware bring-up in a fast-moving AI infrastructure startup.
The Firmware Engineer Tech Lead will architect and develop firmware for SoC and system products, focusing on connectivity solutions for AI infrastructure. The role involves implementing key product features, collaborating with hardware teams, and engaging directly with customers.
Leads post-silicon validation and bring-up of high-speed SerDes (NRZ/PAM4) hardware, debugging mixed-signal issues (jitter, equalization, PLL/CDR) and automating test frameworks with Python/C++ to validate AI infrastructure connectivity chips for hyperscalers.
Lead Astera Labs' offensive security strategy, conducting red teaming and penetration testing across silicon, firmware, systems, and cloud to proactively find and remediate vulnerabilities before adversaries exploit them.
Define and implement end-to-end security architecture for AI infrastructure hardware, firmware, and cloud services at a semiconductor company powering large-scale AI clusters.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Develops firmware and microcontroller subsystems for AI connectivity hardware using C/C++, Python, and RTOS, debugging with JTAG and lab tools in Vancouver.
Intern designs and maintains tools to integrate, debug, and deploy Astera Labs' AI connectivity hardware and software, working with PCIe, Ethernet, CXL, and related technologies.
The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.
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