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At least 7 years of experience in RTL Design verification of SoCs (VHDL, Verilog, System Verilog). At least 2 years of experience in PCIe Logical Phy and PIPE interface pre-silicon verification. Creating System Verilog…

Asic Ethernet PCIe Perl Python +4 skills

SonsoftInc

10 years ago

SoC Design and Verification

Open 47d North AmericaFull-time

United States

In this role, you will anchor the engagement effort for assignments, all the way from business process consulting and problem definition to solution design, development and deployment. You will be pivotal to problem…

Asic Ethernet PCIe Perl Python +5 skills

Collabera

10 years ago

FPGA/RTL Design Engineer – III (W2 Only)

Open 79d North America

United States

Position: FPGA/RTL Design Engineer – III Location: Hillsboro, OR Duration: 4 + Months Job Description: This is a senior RTL design engineer position. Primary responsibilities include: •Working with IP designers and DFx…

FPGA Perl Rtl SystemVerilog Tcl +1 skills

TecTammina

11 years ago

FPGA Design Engineer

Open 47d North AmericaContract

United States

Looking for an FPGA Design Engineer - Consultant to help building a hardware accelerated solutions for its internally developed software at our New York City offices. This candidate will work on a proof of concept…

FPGA Linux PCIe Proof of Concept Verilog

SoC Design and Verification

SoC Design and Verification

FPGA/RTL Design Engineer – III (W2 Only)

FPGA Design Engineer

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SoC Design and Verification

SoC Design and Verification

FPGA/RTL Design Engineer – III (W2 Only)

FPGA Design Engineer