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Senior Staff VLSI Design Engineer coding C++ and SystemC functional models and testbenches for memory/storage products, validating models using SystemC/SV/UVM, debugging firmware issues, and mentoring junior engineers.
Principal Digital Design Engineer owning the architecture and RTL development of a configurable IO subsystem for onsemi's microcontroller platform, using SystemVerilog, Python-based design generators, and UVM verification in Allen, TX.
The Chip Software Engineer will design and build software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation. The role requires strong proficiency in C, C++, and Python to work alongside hardware teams in accelerating silicon development cycles.
The Embedded Semiconductor Engineer will design and build software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation. The role involves working with C, C++, and Python to optimize silicon development cycles and compute-intensive workflows.
A per-diem Security Officer at UVM Medical Center responsible for patrolling, responding to calls for assistance, and documenting services across variable shifts.
The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
This entry-level role involves developing and verifying digital ICs and SoCs for aerospace and defense applications. Engineers will work on FPGA/ASIC design, simulation, and hardware integration using industry-standard tools and HDL languages.
Design Verification Engineer responsible for developing verification plans, test benches, and running regressions to ensure first-pass silicon success for analog and mixed-signal ICs at Texas Instruments in Dallas.
Senior staff engineer verifying AI data-center photonics chips using UVM, AMS, and emulation to ensure designs meet performance and functional goals.
Senior Staff Design Verification Engineer at Lightmatter verifies advanced AI data center photonics and digital/analog designs using UVM, AMS, and emulation, collaborating with cross-functional teams to ensure high-quality chip tapeouts.
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Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
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