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Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.
Role Overview We are seeking a highly experienced Staff Verification Engineer to lead the design verification of next-generation high-speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in…
Principal Design Verification Engineer at Microsoft builds and runs pre-silicon and post-silicon tests for AI accelerators, collaborating with cross-functional teams to verify complex SoC designs using SystemVerilog, UVM, and hardware emulation.
Wir lieben Leidenschaft, Kreativität und Freiraum. Unsere tägliche Arbeit zeichnet sich aus durch individuelle und selbstständige Aufgaben, in der wir viel Raum für eigene Ideen geben. Gemeinsam feiern wir die großen…
Wir bei Capgemini Invent glauben, dass unterschiedliche Perspektiven den Wandel vorantreiben. Als innovative Transformationsberater vereinen wir unsere strategischen, kreativen und wissenschaftlichen Fähigkeiten und…
Senior FPGA engineer designs and deploys low-latency quantum control systems, integrating FPGA hardware with customer setups and troubleshooting quantum experiments.
Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.
Work Model: This is a fully onsite role, with work performed at your designated Regal Rexnord office. ____________________ Du verfügst über fundierte Kenntnisse in der Elektrotechnik, Motorentechnik oder im Bereich…
THE ROLE: You will plan, develop, and execute the SoC verification of new and existing features for AMD’s ASIC and FPGA SoCs, ensuring there are no bugs in the final design. THE PERSON: You have a passion for…
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI,…
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the…
The Senior Design Verification Engineer will verify and optimize digital and analog DRAM circuit designs using tools like SPICE, Verilog, Synopsys, and Cadence Virtuoso. This role involves driving verification planning, circuit simulation, and silicon validation to ensure high-quality memory product delivery.
The Senior FPGA Design Engineer will develop and integrate FPGA designs for surgical robotics systems, focusing on communications, embedded processing, and motor control. The role involves owning designs from concept to production using tools like System-Verilog, AMD Vivado, and Vitis.
Lead end-to-end digital design and verification for mixed-signal SoCs at the Chandler site, driving strategy, methodology standardization (UVM, formal, AMS/DMS), and team scaling.
Principal engineer designing and verifying custom silicon chips for Microsoft's cloud infrastructure, using C/C++, SystemVerilog, UVM, and Python to ensure hardware quality and performance.
Designs and verifies complex ASICs for Google’s TPU hardware, focusing on AI/ML acceleration in data centers. Uses SystemVerilog/UVM to test digital logic, debug designs, and ensure functional correctness for next-gen data center accelerators.
Hey, wir sind Sunlab – schön, dass du vorbeischaust. Du willst SEA nicht nur operativ steuern, sondern strategisch weiterentwickeln, Budgets mit Weitblick führen und echten Impact erzielen? Perfekt – genau das ist…
Design and run AI-driven studies to model and optimize complex defense systems using Python/C++ and simulation frameworks, delivering insights for military and security missions.
Conduct theory- and data-driven studies for simulation-supported operational and mission analysis in military contexts, developing AI/ML algorithms and implementing them in C++ and Python within Airbus's proprietary simulation framework.
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