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Builds and maintains a premium ecommerce site using Shopify/WooCommerce, optimizing performance, features, and customer experience while ensuring SEO and security compliance.
The Java Developer will design and develop high-volume, mission-critical applications using Java and frameworks like Spring Boot. The role involves writing testable code, optimizing performance, and implementing security solutions.
Product Manager on OpenAI's ChatGPT Education & Learning team, defining strategy and building AI-powered learning features across classrooms, careers, and lifelong learning.
Designs and implements firmware/security software for custom silicon, focusing on Root of Trust, secure boot, cryptographic isolation, and hardware/software co-design to protect a new personal computing platform.
Builds and maintains Premium subscription systems (Stripe, Apple/Google IAP, billing, invoicing) to drive conversions and retention, ensuring reliability and scalability for high-value financial transactions.
Leads security and AI governance for an AI services company, ensuring enterprise clients’ systems are trustworthy, compliant, and securely deployed while scaling controls and incident response.
Builds and maintains healthcare platform integrations (APIs, pharmacy networks, health authorities) in a paired engineering environment, focusing on execution, collaboration, and scaling delivery for a cloud-based pharmacy service platform.
Lead a hardware engineering team at a NASDAQ-listed AI connectivity company, designing high-speed cables, modules, and rack-scale systems while enabling OEM customers to integrate Astera Labs' silicon into their products.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Principal Product Manager at Astera Labs in San Jose defines and drives the Smart Cable Modules product line, collaborating with hyperscalers to deliver high-bandwidth connectivity solutions for AI and cloud infrastructure using PCIe, Ethernet, CXL, and related technologies.
Leads the product strategy for a unified management suite that orchestrates software, firmware, and silicon across Astera Labs' AI connectivity products, focusing on PCIe, CXL, and Ethernet technologies.
Senior engineer validates AI connectivity SoCs on emulation platforms, debugging high-speed interfaces like PCIe and Ethernet before silicon tape-out.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Designs and runs tests to validate high-speed semiconductor chips (CXL, PCIe, Ethernet) for AI infrastructure, ensuring reliability and performance in server/storage systems.
Lead Astera Labs' offensive security strategy, conducting red teaming and penetration testing across silicon, firmware, systems, and cloud to proactively find and remediate vulnerabilities before adversaries exploit them.
Define and implement end-to-end security architecture for AI infrastructure hardware, firmware, and cloud services at a semiconductor company powering large-scale AI clusters.
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