Leads Normal Computing's physical design team in Silicon Valley, owning the end-to-end backend ASIC flow from synthesis, floorplanning, and place-and-route through STA timing closure, DRC/LVS signoff, and GDSII tapeout, while hiring, planning tapeout schedules, and collaborating with RTL/architecture teams using tools like Innovus, PrimeTime, and Calibre.
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