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Staff Digital Design Engineer responsible for FPGA/ASIC RTL design, board-level schematic capture, and system architecture for aerospace and defense applications (electronic warfare, radar, communications) using Verilog/VHDL, high-speed interfaces, and PCB tools.
Senior Staff Engineer performing physical design (place-and-route, static timing, physical verification) on next-generation high-performance processor/ASIC chips using EDA tools, with automation scripting in Shell, Python, and TCL.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our…
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
Designs and optimizes FPGA-based digital signal processing for RF systems, translating algorithms into real-time HDL implementations while collaborating with hardware and software teams in a space-focused startup.
Designs and develops data readout methodologies for advanced CMOS image sensors (e.g., CIS300) to support space missions (e.g., SMILE, NewAthena). Focuses on high-data-rate handling, HDR, and non-destructive readout techniques, interfacing detectors with on-board processing systems and collaborating with scientists/engineers to ensure data usability.
Design and implement FPGA/ASIC applications using OCaml and Hardcaml (an OCaml RTL library) for RTL design and testing, with some Verilog and C work, at a quantitative trading firm.
Interns collaborate with full-time engineers on FPGA/ASIC hardware projects using OCaml and Hardcaml, from design to validation, with mentorship and exposure to Jane Street’s internal tools.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
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