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Lead ASIC design verification for complex networking SoCs at Cisco's Common Hardware Group, planning and executing verification strategies, mentoring engineers, and building scalable SystemVerilog/UVM environments across silicon development.
Design verification engineer building and running SystemVerilog/UVM testbenches to validate ASIC/FPGA/SoC designs for aerospace systems in El Segundo or Huntington Beach, CA.
Staff engineer builds formal verification environments and properties to exhaustively validate next-gen mobile GPU blocks, ensuring functional correctness and power gating for Samsung’s Xclipse GPU.
Chip Design Verification Engineer verifying and simulating performance and power management IPs using RTL verification methodologies, in close collaboration with design and architecture teams at NVIDIA.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Own verification of custom AI accelerator hardware for matrix/vector compute engines, ensuring numerical correctness and performance under LLM workloads using SystemVerilog/UVM and reference models.
Designs and executes verification plans for a custom Physical AI SoC’s CPU, ensuring correctness, performance, and reliability of microarchitecture components (fetch/decode/cache) via SystemVerilog/UVM/C++ testbenches and real-world workload testing.
Lead pre-silicon verification for SambaNova’s AI chips, owning methodology, testbenches, and tape-out readiness, then debug first silicon in the lab.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Design Verification Engineer verifying complex internal IP blocks (compute engines, accelerators, custom logic) within SoC environments using UVM-based verification, 5 days onsite in San Jose.
Ort: 99192 Neudietendorf | Vertragsart: Voll-/Teilzeit, unbefristet | Job-ID: 975157 Dein Home of IT: REWE digital Wir sind das Zuhause für alle, die sich in der digitalen Welt tummeln. Ein Tech-Team, in dem IT- und…
in dieser abwechslungsreichen Position hautnah an unseren Kunden und bist durch die enge Zusammenarbeit mit dem Vertriebsteam und dem Produkt Team ein wichtiger Teil unseres Vertriebsprozesses. Du punktest mit…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Designs and executes verification testbenches for memory interface chips using System Verilog and UVM to ensure 100% coverage before tape-out.
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
Principal Logic Design Engineer responsible for micro-architecture and RTL design of next-generation high-performance memory controllers for data centers and AI applications, using SystemVerilog/Verilog and collaborating with verification and physical design teams.
Designs and runs RTL validation for Intel’s IP blocks, using System Verilog and UVM to verify DDR5/LPDDR5 and debug failures before tape-out.
This role involves verifying and analyzing complex full-chip gate-level custom memory designs, including DDR and LPDDR architectures. The engineer will utilize AI-based tools, automation frameworks, and simulation environments to accelerate verification cycles and improve debug efficiency.
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