Tech jobs

New HybridUK H-1B sponsor history

Digital Design Engineer (TR-NWB)

United Kingdom

Cirrus Logic is hiring a Digital IC Design Engineer in Newbury, UK to design and develop digital circuit architectures and SoCs for consumer mixed-signal products — taking blocks from concept through RTL design, verification, and synthesis to production, and mentoring junior engineers.

Automation Cmos I2c MATLAB Microcontrollers +3 skills

Analog Design Engineer

Cmos MATLAB Signal Processing Simulink SystemVerilog +1 skills

Analog Design Engineer at Cirrus Logic in Austin, TX (hybrid): designs analog/mixed-signal IC blocks — data converters, power management, amplifiers — in advanced CMOS, owning architecture, transistor-level design, simulation (Spectre, Matlab, Verilog-A), layout closure, and silicon bring-up through production.

Digital Design Engineer

Digital Design Engineer at Cirrus Logic in Austin, TX: design and implement digital subsystems and IP blocks for mixed-signal ICs — SoC devices, DSP blocks, and control logic — in Verilog RTL from architecture through tape-out, supporting verification, silicon bring-up, and debug alongside analog and test teams.

Design Verification Engineer

Asic Automation Firmware Signal Processing SystemVerilog +3 skills

Cirrus Logic is hiring a Design Verification Engineer in Austin to verify mixed-signal ASICs at block and chip level — building UVM testbenches, driving coverage closure, running gate-level simulations, and debugging regressions. Core stack: Verilog/VHDL, SystemVerilog with UVM, plus exposure to formal verification and emulation.

Senior Analog Design Engineer

Cmos MATLAB Signal Processing Simulink SystemVerilog +1 skills

Senior analog design engineer at Cirrus Logic in Austin (hybrid) designing high-performance analog/mixed-signal IC blocks — data converters, power management, amplifiers — in advanced CMOS, owning the full IC lifecycle from architecture and transistor-level design (Spectre, Matlab, Verilog-A) through layout closure and silicon bring-up/lab validation.

Applications Engineer (JN-64001161)

Firmware Git I2c MATLAB Oscilloscope +6 skills

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top…

New HybridUK H-1B sponsor history

Digital Design Engineer (AP)

United Kingdom

Digital IC Design Engineer at Cirrus Logic in Edinburgh, developing digital circuit architectures and block-level testbenches for mixed-signal SOCs targeting global consumer mobile markets. Day to day is RTL design/verification with Verilog/SystemVerilog, synthesis, timing analysis and CDC/RDC linting; hybrid role with 2+ days in office.

Automation Cmos FPGA I2c MATLAB +4 skills

Senior Design Verification Engineer (BO - 01)

Signal Processing SystemVerilog Uvm Verilog VHDL

Senior Design Verification Engineer at Cirrus Logic in Chandler, AZ, verifying complete mixed-signal IC developments: verification planning, UVM testbench development, coverage and failure analysis, digital/mixed-signal modeling, and regression/infrastructure support. Core stack: Verilog/VHDL and SystemVerilog/UVM.

Senior Staff Analog Design Engineer

Cmos MATLAB Signal Processing Simulink SystemVerilog +1 skills

Cirrus Logic in Austin is hiring a Senior Staff Analog Design Engineer to design high-performance analog and mixed-signal IC blocks (data converters, power management, amplifiers) in advanced CMOS — covering architecture, transistor-level design, simulation with Spectre/Matlab, layout closure, and silicon bring-up through production.

Staff Analog Design Engineer

Cmos MATLAB Signal Processing Simulink SystemVerilog +1 skills

Designs analog and mixed-signal IC blocks (data converters, power management, amplifiers) in advanced CMOS at Cirrus Logic in Austin, owning blocks from architecture and transistor-level design through simulation, layout closure, and silicon bring-up. Core tools include Matlab, Spectre, Verilog-A/SystemVerilog, and Simulink.

Senior Staff Design Verification Engineer

Asic Automation Firmware Signal Processing SystemVerilog +3 skills

Senior design verification engineer at Cirrus Logic in Austin performing end-to-end block- and chip-level functional verification of mixed-signal ASICs — building UVM testbenches, driving coverage closure, debugging gate-level simulations, and supporting pre- and post-silicon validation using SystemVerilog/Verilog.

Staff Design Verification Engineer

Asic Automation Firmware Signal Processing SystemVerilog +3 skills

Staff Design Verification Engineer at Cirrus Logic in Austin (hybrid) performing end-to-end functional verification of mixed-signal ASICs at block and chip level. Day-to-day work centers on UVM/SystemVerilog testbenches, coverage closure, regression triage, gate-level simulation, and pre/post-silicon validation alongside design, firmware, and test teams.

Senior Design Verification Engineer

Asic Automation Firmware Signal Processing SystemVerilog +3 skills

Senior design verification engineer at Cirrus Logic performing end-to-end verification of mixed-signal ASICs: building UVM testbenches, driving functional/code coverage closure, debugging regressions and gate-level simulations, and supporting pre- and post-silicon validation with design, firmware, and test teams. Core tech: SystemVerilog/UVM, Verilog/VHDL.

Senior Staff Digital Design Engineer

Designs and verifies digital subsystems (RTL in Verilog, DSP blocks, control logic) for Cirrus Logic's mixed-signal SoCs — chips interfacing with ADCs, DACs, amplifiers, and power management — from architecture through tape-out, including post-silicon validation and lab debug.

Staff Digital Design Engineer

Staff Digital Design Engineer at Cirrus Logic in Austin designs and verifies digital subsystems — RTL, DSP, control and data-path logic — for mixed-signal SoCs, taking them from architecture through tape-out and silicon debug. Core technologies: Verilog, UVM verification, CMOS VLSI, and tools like MATLAB/Simulink.

Senior Digital Design Engineer

Designs digital subsystems and IP blocks for mixed-signal ICs and SoCs at Cirrus Logic — taking DSP, control, and data-path logic from microarchitecture through RTL, verification, synthesis, and post-silicon debug. Core stack: Verilog RTL, digital design flow, UVM verification, CMOS VLSI, and DSP modeling.

Apple

New EuropeInternshipIntern

Cellular Baseband Design Verification Intern

Germany

Internship with Apple's Cellular Baseband DV team in Munich: verifying baseband modems and RF link controllers for Apple's SoCs by building reusable UVM environments and coverage-driven/directed tests. Core stack is SystemVerilog/Verilog, UVM, C/C++, and Python, with exposure to 4G/5G (3GPP) protocols, low-power architectures, and LLM-based tooling.

Asic Automation C++ Firmware LLM +7 skills

General Dynamics UK

AI Embedded Software Embedded Systems Firmware FPGA +4 skills

FPGA Design Engineer

New HybridUK

United Kingdom

Develop and integrate FPGA-based solutions (VHDL/Verilog) for safety-critical mission computing on the UK's next-generation combat aircraft programme within General Dynamics UK's TEMPEST team — covering the full lifecycle from requirements and design to simulation, verification and integration.

36K – 45K £

FIRST RF

New North AmericaFull-time

Embedded Systems Engineer