Senior CAD engineer who owns pre-silicon front-end automation at a custom silicon startup: RTL design flows, DV simulation/regression flows, emulation and FPGA prototyping, keeping those flows reliable from RTL entry through DFT handoff. Core tech: SystemVerilog, Python, Linux/LSF/Slurm, Synopsys/Cadence/Siemens EDA tools, plus AI-assisted tooling.
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