Principal Field Applications Engineer at Astera Labs designs and supports AI infrastructure connectivity solutions for cloud providers and OEMs using CXL, Ethernet, PCIe, and related technologies.
Lead a new Taiwan hardware engineering hub to design validation platforms and rack-scale systems for AI connectivity, while partnering with OEMs across Asia to integrate Astera Labs’ silicon into their products.
Lead a hardware engineering team at a NASDAQ-listed AI connectivity company, designing high-speed cables, modules, and rack-scale systems while enabling OEM customers to integrate Astera Labs' silicon into their products.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Principal Field Applications Engineer designs and supports AI connectivity solutions for cloud providers and OEMs, focusing on PCIe, Ethernet, and CXL technologies.
Principal firmware engineer at Astera Labs, building and debugging C/Python code for CXL and DDR memory subsystems while acting as the technical liaison for hyperscale customers and OEMs.
Principal Product Application Engineer at Astera Labs designs and troubleshoots PCIe connectivity solutions for AI infrastructure, working with hyperscalers and OEMs to deploy high-speed retimers and influence product direction.
Principal Product Applications Engineer at Astera Labs designs and troubleshoots high-speed Ethernet connectivity for AI infrastructure, working directly with customers to deploy Taurus Smart Cable Modules in data centers.
Principal Silicon Validation Engineer at Astera Labs in San Jose, CA designs and executes electrical tests to validate AI connectivity hardware, using PCIe, Ethernet, and CXL technologies.
Principal Test Engineer at Astera Labs designs and implements automated test solutions for high-speed mixed-signal silicon SoC products, using protocols like PCIe, Ethernet, and DDR, and oversees production ramp.
Quality Engineer driving root-cause analysis of failures across semiconductor circuit, package, firmware, and protocol layers for PCIe and Ethernet connectivity solutions. Uses advanced lab instrumentation (BERT, oscilloscopes, VNAs, TDR) to debug high-speed SERDES and collaborates cross-functionally to ensure product reliability for AI infrastructure hardware.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Designs and leads RTL implementation for AI infrastructure silicon, focusing on PCIe, CXL, Ethernet, and emerging interconnects to deliver high-performance connectivity solutions.
Designs and implements RTL for high-speed interconnect silicon (PCIe, CXL, Ethernet) that powers AI infrastructure, shepherding blocks from spec to tapeout.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Test Engineer at Astera Labs' semiconductor assembly and test facility in Aachen: executing production test programs on automated test equipment, debugging hardware/software failures, analyzing yield data, and supporting new product introduction. Requires an EE-related degree, basic scripting (Python/C++/LabVIEW), and lab instrumentation skills.