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RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
An ASIC digital engineer specializing in FPGA prototyping, emulation, and system-level debugging to support platform bring-up, hardware/software co-verification, and end-user collaboration.
Lead functional verification for complex IP blocks and SoC designs using System Verilog and UVM frameworks, focusing on NAND flash memory verification at Sandisk.
Senior Staff VLSI Design Engineer coding C++ and SystemC functional models and testbenches for memory/storage products, validating models using SystemC/SV/UVM, debugging firmware issues, and mentoring junior engineers.
General Dynamics Electric Boat is seeking hardware and software engineers to develop and integrate electric drive propulsion control systems for U.S. Navy submarines. The role involves embedded software development, hardware design, and rapid prototyping using languages like C, C++, and Python.
The Senior ASIC Design Engineer will architect and design high-performance networking ASICs, focusing on micro-architecture, logic design, and power optimization. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
The Senior ASIC Design Engineer will architect and design high-performance networking ASIC blocks, focusing on micro-architecture, logic design, and power efficiency. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
Be visionary Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory…
Role Purpose The Physical IP Division in Arm Noida creates Memory IPs which are extensively used by thousands of SoC designers around the world to design leading edge chips. We are currently developing memory fast…
Nokia of America Corporation , Sr ASIC Physical Design Engineer (Multiple Positions), Sunnyvale, CA. Support specification, design, and implementation of digital hardware, applying design targets related to cost,…
Lead FPGA firmware engineer designing and developing Control & Protection systems for HVDC projects (VSC/LCC), focusing on FPGA firmware in VHDL/Verilog, model-based design with MATLAB/Simulink, and high-speed digital hardware design.
DSP Hardware Design Engineer at Cadence responsible for CPU/DSP/NPU hardware accelerator design and tape-outs using Verilog/SystemVerilog, EDA tools, and Perl scripting.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview As a Senior Principal Design Engineer, you will be responsible for the design,…
Physical design intern working on next-generation high-performance processor ASIC physical design and methodology using cutting-edge CMOS process technology for server, 5G/6G, automotive, and networking applications.
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: SAP TRAVEL: No Description At Northrop Grumman, our employees have incredible opportunities to work on…
Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and…
Job Description: 1. Responsible for micro-architecture design and RTL implementation of high-performance CPU front-end pipeline, including instruction fetch, branch prediction, instruction decode, dispatch and…
The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
The SoC Digital Design Engineer will design and implement hardware accelerators for video codecs and SoC subsystems using Verilog/SystemVerilog. The role involves architecture definition, RTL implementation, and cross-functional collaboration to optimize power, performance, and area for large-scale video platforms.
Designs and optimizes DRAM circuits using CMOS logic and AI-enabled tools, leading layout and simulations to deliver high-performance memory solutions.
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