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Designs and architects System-on-Chip IP blocks, defining roadmaps and guiding cross-functional teams through development, verification, and validation for next-gen ASICs.
Dein Team Du denkst in Konzepten, nicht nur in Posts? Du entwickelst Formate, die hängen bleiben, und weißt, wie man digitale Produkte in Stories verwandelt, die sich anfühlen wie OMR Education, nicht wie Werbung? Dann…
Dein Team Du möchtest nicht nur Newsletter verschicken, sondern CRM als Wachstumstreiber weiterentwickeln? Du denkst in Customer Journeys, Marketing Automation und datenbasierten Entscheidungen? Dann bist du bei OMR…
Designs and implements FPGA-based prototypes for ASIC validation using Verilog, high-speed interfaces, and Quartus Prime Pro, collaborating with cross-functional teams to optimize timing and debug hardware.
Lead verification of high-bandwidth memory (HBM) and DRAM designs using SystemVerilog/UVM, ensuring functional correctness and performance for Micron’s memory products.
Wir sind mehr als eine Agentur für mehr als eine Bank. Wir sind der zentrale Partner für Kommunikation und digitale Services in der Sparkassen-Finanzgruppe. Mit mehr als 600 Mitarbeiter:innen vernetzt die S-Com…
Design Verification Engineer builds and verifies RTL components in Verilog/SystemVerilog to improve AI model training and evaluation workflows, using UVM and LLM-based tools.
Arquitecto en Cibersegurida d En este rol serás responsable de diseñar, implementar y evolucionar la arquitectura de seguridad tecnológica, asegurando la integración de controles desde el diseño (“Secure by Design”) en…
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
Unsere Größe und fachliche Breite ermöglichen dir Gestaltungsspielraum über die gesamte Klaviatur des Marketings hinweg: Strategie, Positionierung & Employer Branding: Du entwickelst unsere Marketingstrategie und…
Verify custom silicon designs for Google Cloud, building constrained-random test environments in SystemVerilog/UVM to uncover bugs and ensure tape-out readiness.
Architect and lead formal verification strategies for complex ASIC designs, guiding teams to ensure silicon quality for next-gen processors and I/O technologies.
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Lead verification of AMD’s IOHUB subsystem, defining test plans and collaborating with global teams to ensure high-performance interconnect IP meets design specs.
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Verify next-gen PCIe controller designs for AMD’s SoCs, using SystemVerilog/UVM testbenches and low-power techniques to ensure performance and power targets for AI, gaming, and server chips.
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Design and verify next-gen ASICs using SystemVerilog and UVM, collaborating with architects and engineers to ensure first-pass silicon success.
Design Verification Engineer at AMD builds and runs testbenches in SystemVerilog/UVM to validate DDR5/LPDDR5 memory interfaces and DFI protocols for server products.
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
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