Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Staff FPGA Developer architecting reconfigurable logic for spacecraft avionics and payload systems, leading a real-time FPGA-based image processing pipeline for on-orbit detection and tracking using VHDL/Verilog.
This role involves developing and scaling an AI-assisted silicon design framework using agentic ecosystems, RAG, and LLM orchestration. The engineer will build production-ready AI workflows to automate and optimize the silicon IP development lifecycle.
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior engineer validates AI connectivity SoCs on emulation platforms, debugging high-speed interfaces like PCIe and Ethernet before silicon tape-out.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Designs and implements digital blocks for semiconductor chips powering AI infrastructure, using Verilog/SystemVerilog and RTL coding principles with industry EDA tools.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.
Designs FPGA logic for high-speed trading systems, optimizing performance and ensuring timing closure while managing the full development lifecycle from coding to deployment.
Principal Design Verification Engineer at Microsoft builds and runs pre-silicon and post-silicon tests for AI accelerators, collaborating with cross-functional teams to verify complex SoC designs using SystemVerilog, UVM, and hardware emulation.
The Senior Digital Design Engineer will design and implement FPGA architectures and DSP algorithms for real-time defense applications. The role involves high-speed interface integration, system-level architecture decisions, and close collaboration with hardware and software teams.
Backend engineer responsible for synthesis (RTL to gate-level), DFT tasks (scan insertion, ATPG, MBIST), and STA/timing closure on large-scale chips at 28nm or below, collaborating with RTL and PnR teams.
Ingeteam , empresa líder especializada en ingeniería eléctrica y en el desarrollo de equipos eléctricos, motores, generadores y convertidores de frecuencia busca incorporar un/a Ingeniero/a de Diseño FPGA para…
Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.
Designs and optimizes next-gen NAND Flash storage systems using FPGA architectures, focusing on RTL development, IP integration, and system validation for high-performance digital solutions.
Staff Digital Design Engineer responsible for all aspects of digital design in 3D NAND Flash memory, including micro architecture, RTL design in Verilog, verification, synthesis, DFT, and timing analysis from RTL to GDSII.
We couldn't check your fit for this role — add a CV to your profile to see it next time.