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Principal Silicon Validation Engineer at Astera Labs in San Jose, CA designs and executes electrical tests to validate AI connectivity hardware, using PCIe, Ethernet, and CXL technologies.
Principal Silicon Validation Engineer designs and runs electrical tests to verify high-speed connectivity chips (PCIe, PAM4 Ethernet) meet strict performance margins for AI infrastructure products.
Leads supplier quality engineering for AI connectivity hardware, partnering with global manufacturers to ensure product quality and reliability using advanced analytics and AI/ML tools.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Leads the product strategy for a unified management suite that orchestrates software, firmware, and silicon across Astera Labs' AI connectivity products, focusing on PCIe, CXL, and Ethernet technologies.
Senior engineer validates high-speed connectivity chips and boards for AI data centers, designing automated tests for CXL, PCIe, and Ethernet compliance and performance.
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Leads validation and characterization of advanced photonic integrated circuits (PICs) integrated with electronic ICs for high-speed data center and AI applications, using optical and electrical testing tools.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Principal Analog Design Engineer at Astera Labs designs high-performance analog and mixed-signal circuits for AI connectivity hardware in San Jose, CA.
Leads post-silicon validation and bring-up of high-speed SerDes (NRZ/PAM4) hardware, debugging mixed-signal issues (jitter, equalization, PLL/CDR) and automating test frameworks with Python/C++ to validate AI infrastructure connectivity chips for hyperscalers.
Define and implement end-to-end security architecture for AI infrastructure hardware, firmware, and cloud services at a semiconductor company powering large-scale AI clusters.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
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