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Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Designs mechanical installations for military aircraft systems, creating certified designs optimized for weight, cost, and safety while coordinating with engineering teams and suppliers.
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms.…
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Designs and verifies mixed-signal ICs, building simulation environments and automated regressions to ensure silicon meets specs before tapeout and aligns with customer needs.
Design and verify custom TPU silicon for Google’s AI workloads using SystemVerilog/UVM, driving full verification cycles from planning to tape-out.
Develop and maintain HMI applications for packaging machines, focusing on usability and user experience, and support global customer deployments.
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Verify next-gen PCIe controller subsystems for AMD’s SoCs, using UVM, SystemVerilog, and low-power flows to ensure performance and power targets for AI, gaming, and server chips.
Wir sind Evernest – das Immobilienunternehmen, das Technologie und persönliche Beratung auf höchstem Niveau vereint. Mit digitalen Tools, maßgeschneiderten Marketingstrategien und tiefem lokalen Marktverständnis machen…
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
Lead FPGA verification for safety-critical avionics under DO-254, defining test strategies and ensuring FAA/EASA certification readiness with UVM, SystemVerilog, and VHDL.
Design and verify PCIe interconnect IP for AMD’s GPUs, APUs, servers, and consoles using UVM/SystemVerilog, collaborating with global teams.
Designs and verifies safety-critical GPU hardware for automotive and robotics, ensuring compliance with ISO 26262 through safety analyses and documentation.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Verification Application Engineer (AE) at Cadence you will be responsible for leading customer…
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