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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Verification Application Engineer (AE) at Cadence you will be responsible for leading customer…
With around 9,000 employees, AGRANA is the global leader in fruit preparations and also a major producer of fruit juice concentrates in Europe as well as being a key manufacturer of customised starch products and…
Building Name: UVMMC - 1 South Prospect StreetLocation Address: 1 South Prospect, Burlington VermontRegularDepartment: Addiction MedicineFull TimeStandard Hours: 40Biweekly Scheduled Hours: 80Shift: Day-8HrPrimary…
Leads full-chip functional verification for Micron’s non-volatile memory designs using System Verilog, UVM, and coverage-driven methodology to ensure tape-out readiness.
Design and verify high-speed networking silicon chips, ensuring low latency and high throughput for NVIDIA's communication devices.
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, synthesis, and verification flows.
Staff Subsystem Design Engineer Job Overview Arm’s IP and Technology team in Solutions Engineering department evelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud…
Architect and optimize the next-generation SystemVerilog compiler for Xcelium, enabling faster verification of billion-gate AI and hyperscale chip designs using C++ and compiler theory.
Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
Design and verify FPGA hardware using VHDL for radar, RF/EO DSP, and embedded systems; collaborate with systems engineers and verify designs with constrained-random tests.
Design and run verification tests for next-gen DRAM and memory chips using SystemVerilog/UVM, debug failures, and automate flows to ensure silicon meets specs.
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
Lead verification of AMD’s IOHUB subsystem, defining test plans and closing coverage for high-performance interconnect IP used in CPUs, GPUs, and data-center hardware.
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.
Designs and writes advanced circuit-engineering free-response questions to stress-test AI models, requiring a PhD in EE and 5+ years of shipped analog/digital/power/RF designs.
Design and implement AI/LLM solutions for enterprise products, including strategy, architecture, and scalable platforms with RAG, agents, and workflows.
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Legacy verstehen. Zukunft bauen. Du kennst IBM i nicht nur aus der Theorie, sondern weißt, wie geschäftskritische Anwendungen über Jahre und Jahrzehnte gewachsen sind? Gleichzeitig hast du Lust, bestehende Software…
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Regulatory Affairs - Identifizieren und abstimmen von legalen Anforderungen zur Beurteilung qualitätsrelevanter Eigenschaften und Produktkennzeichnung für den internationalen Vertrieb Qualitätsprüfung - Sicherstellen…
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