SMTS Package Design Engineer at AMD Singapore leading advanced semiconductor packaging design (2.5D/3D, chiplets, interposers, substrate layouts) for high-performance computing and AI products. Requires 8+ years of experience with EDA tools like Cadence SIP/APD and Synopsys 3DICC, working cross-functionally with SI/PI, mechanical, and SOC teams to deliver complex heterogeneous integration solution
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