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Application Engineer I: Systems Verification - Emulation Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Design and implement firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.
Lead verification of low-power SoC features using UPF/CPF, building SystemVerilog/UVM testbenches and power-aware test plans to ensure robust, energy-efficient silicon.
Design and implement FPGA-based digital logic using VHDL/Verilog, integrate custom IP cores, and optimize designs for performance and timing closure.
Lead the verification of custom silicon chips powering Google’s consumer products, coordinating cross-functional teams to ensure bug-free SoC tape-outs using formal, UVM, and C-based testing.
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
Designs and verifies digital IP blocks and SoC architectures using SystemVerilog/UVM to ensure functional correctness of high-speed ASIC components like Ethernet switches and PCIe controllers.
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
Designs and builds software tooling, firmware, and infrastructure to accelerate semiconductor development cycles, working closely with hardware teams in EDA, verification, or post-silicon environments using C, C++, and Python.
Lead formal verification for AMD’s I/O and SoC designs, defining methodologies and mentoring engineers to ensure silicon quality for next-gen processors and AI systems.
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training…
Design verification engineer building and testing TPU silicon for Google’s AI/ML workloads using SystemVerilog and UVM.
Lead verification of high-speed DSP pipelines for Google’s TPU AI accelerators, ensuring pre-silicon models match physical silicon behavior using SystemVerilog/UVM and emulation.
Senior engineer verifying next-gen microprocessor interconnects using SystemVerilog/UVM testbenches and industry tools to ensure functionality and performance before silicon tape-out.
Builds and maintains AWS-based cloud infrastructure, deploys containerized workloads with Docker/Kubernetes, and supports CI/CD pipelines for a Swiss laundry-tech manufacturer.
Build ML models and synthetic data pipelines to improve chip-design workflows, collaborating across AI, hardware, and software teams.
Build and refine the frontend of a cutting-edge asset-management platform using Angular 21, TypeScript, and a custom component library, while mentoring peers and shaping UI/UX for complex financial data.
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