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We’re here for one reason and one reason only – to cure cancer. Every moment is dedicated to developing treatments and every action moves us one step closer to our goal. We’ve made incredible scientific breakthroughs…
Designs analog, mixed-signal, and RF circuit blocks for Silicon Labs' low-power wireless connectivity SoCs, taking them from architecture and simulation through layout guidance, prototype testing, and production support. Core stack is CMOS analog design (bandgap, LDO, ADC/DAC, PLL, oscillators, TX/RX) with VerilogA/AMS modeling.
BeOne continues to grow at a rapid pace with challenging and exciting opportunities for experienced professionals. When considering candidates, we look for scientific and business professionals who are highly…
About Reputation Reputation, founded in Silicon Valley in 2013, is the industry's sole platform that uses an AI-powered product stack to help companies measure, manage, and scale their real-time reputation…
Lead a team of analog IC design engineers at Semtech's Bristol office, developing laser driver, TIA, and transceiver ICs for optical communications in FTTH and datacentre networks. Hybrid role (office Mon-Thu) blending people management, project delivery, and hands-on technical guidance across SiGe BiCMOS and CMOS processes.
Category: Health Care Location: The CodingQuality Auditor and Specialist is responsible for assuring coding guidelinesand regulations are not compromised during the decision-making process relatedto clinical…
PTC Therapeutics is a global commercial biopharmaceutical company. For over 25 years our team has been deeply committed to a unified purpose: Extending life’s moments for children and adults living with a rare disease.…
(This is for a RevPilots' client) Our client is transforming commerce with end-to-end AI that unifies discovery, conversations, and checkout into a single intelligent system that delivers autonomous, intent-driven…
The Asahi Kasei Group operates with a commitment of creating for tomorrow. Our business sectors, Materials, Homes, and Health Care , contribute to the development of society by anticipating the changing needs of those…
About SpangleAI Launched in 2025, Spangle AI helps enterprise retailers win AI-driven product discovery, connecting discovery to conversion. We've partnered with enterprise brands like REVOLVE, Alexander Wang, and…
Tech Lead for front-end digital design of high-performance switch ASICs powering rack-scale AI infrastructure at Astera Labs. The role owns blocks from microarchitecture through GDS — RTL, synthesis, timing closure, gate-level simulation, DFT, verification, and silicon bring-up — using Synopsys/Cadence flows and protocols like PCIe Gen 6/7, Ethernet, UALink, and UCI.
Astera Labs is hiring a Tech Lead Digital Design Engineer in San Jose to lead micro-architecture and front-end design (RTL, synthesis, IP integration, block-level verification) of high-performance network controllers for its AI connectivity silicon. Core work spans PCIe/Ethernet/UALink protocols, Synopsys/Cadence flows, DFT, and silicon bring-up.
Principal Analog Design Engineer who architects and designs high-speed analog/mixed-signal circuits (PLLs, SerDes building blocks, ADCs/DACs, references, clocking) for Astera Labs' AI connectivity silicon, owning designs from spec through layout and silicon bring-up in advanced FinFET nodes, using Cadence Virtuoso/Spectre and mentoring the analog team.
Astera Labs is hiring a Principal Digital Design Engineer in San Jose to own front-end silicon design of high-performance network controllers/switch ASICs — micro-architecture, RTL, synthesis, IP integration, DFT, and block-level verification, through production and silicon bring-up. Core technologies include PCIe, Ethernet, UALink, Synopsys/Cadence flows, and UVM.
Hands-on principal-level analog IC designer at Astera Labs who architects high-speed analog/mixed-signal circuits (PLLs, SerDes, ADCs/DACs, clocking) for AI infrastructure connectivity silicon in advanced FinFET nodes, owning designs from spec through silicon bring-up while setting methodology and mentoring the analog team in San Jose.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
About AllCloud AllCloud is a leader in amplifying organizations’ cloud potential through AI. With a track record of hundreds of successful migrations and implementations across AWS and Salesforce, AllCloud has…
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…
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