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Astera Labs Early Career - North America 2027
6 views 19 hours ago

AMS Digital Design Engineer Intern

NewBe an early applicant North AmericaInternshipIntern
United States

Digital RTL Design Engineer – Intern Role overview Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and…

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Astera Labs Early Career - North America 2027
3 views 19 hours ago

AMS Digital Design Engineer NCG

NewBe an early applicant North America
United States

Digital RTL Design Engineer – NCG Role overview Astera Labs is seeking a motivated Digital RTL Design Engineer to join our San Jose design team. This is an opportunity for a new college graduate to build ownership in…

AI Asic Bash Cloud Ethernet +10 skills
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Astera Labs
13 views 19 hours ago

Physical Design Student

Open 139d MENA H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.

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Astera Labs
9 views 19 hours ago

Principal Physical Design Engineer, STA

Open 139d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

AI Automation Cloud Ethernet Networking +8 skills
209K – 250K $
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Astera Labs
13 views 19 hours ago

Senior ASIC Design Engineer

Open 139d MENASenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.

AI Asic Automation Ethernet PCIe +5 skills
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Astera Labs
9 views 19 hours ago

Staff/ Principal Physical Design STA Engineer

Open 139d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.

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Astera Labs
11 views 19 hours ago

SoC Design Director

Open 122d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.

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Astera Labs
16 views 19 hours ago

Technical Lead Physical Design Engineer

Open 119d On-siteNorth AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.

AI Automation CAD Cloud Ethernet +9 skills
140K – 180K CAD
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Astera Labs
12 views 19 hours ago

Staff / Principal ASIC Design Engineer

Open 105d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

AI Asic Automation Ethernet PCIe +5 skills
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Astera Labs
11 views 19 hours ago

Principal Physical Design Engineer, Methodology

Open 98d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.

Agentic AI AI Automation CAD CI/CD +5 skills
185K – 240K $
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Astera Labs
12 views 19 hours ago

Tech Lead ASIC Design Engineer

Open 90d APACLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads the design and implementation of high-performance digital IPs and SoC subsystems for AI infrastructure connectivity chips using Verilog/SystemVerilog, CXL, PCIe, and Ethernet.

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Astera Labs
10 views 19 hours ago

Senior Physical Design Engineer

Open 86d APACSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Leads physical design for next-gen transceiver IPs on TSMC 3nm nodes, handling floorplanning, placement, CTS, routing, and verification to ensure timing/power/area convergence with RTL and STA teams.

AI Automation Ethernet PCIe Perl +3 skills
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Astera Labs
10 views 19 hours ago

STA Physical Design Engineer, Senior Principal

Open 57d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Senior principal physical design/STA engineer who owns RTL-to-GDS delivery—place-and-route, static timing analysis, and full-chip signoff (extraction, EM-IR, Formality, DRC/LVS)—for Astera Labs' connectivity ASICs used in AI/cloud infrastructure, using Cadence/Synopsys toolchains, PT DMSA ECO flows, and SDC constraints. Fully on-site in San Jose.

AI Cloud Ethernet Networking PCIe +6 skills
207K – 230K $
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Astera Labs
19 views 19 hours ago

Senior Digital Design Engineer

Open 48d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

A Senior Digital Design Engineer at Astera Labs designs high-performance connectivity silicon for AI infrastructure, owning micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe/Ethernet controllers, bridges, switches, and SerDes interfaces. Core tech includes SystemVerilog/Verilog, Synopsys and Cadence tools, and Python/Perl automation.

AI Automation CAD CI/CD Embedded Software +11 skills
140K – 155K CAD
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Astera Labs
10 views 19 hours ago

Senior Design Verification Engineer

Open 47d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Builds and maintains UVM-based verification environments (SystemVerilog with C/C++ via DPI/PLI) for connectivity silicon used in rack-scale AI infrastructure, writing tests, assertions, and coverage while debugging across simulation, co-simulation, and FPGA emulation alongside RTL designers.

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Astera Labs
9 views 19 hours ago

Design Verification Tech Lead- SerDes/PHY IP

Open 37d North AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal-level design verification tech lead owning functional verification of high-speed SerDes/PHY IP for AI infrastructure connectivity. Day to day: architecting UVM testbenches, driving coverage closure to tape-out, verifying against PCIe Gen 6/7, UALink, UCIe, and Ethernet PHY specs, and mentoring DV engineers. Core stack: SystemVerilog/UVM, analog/mixed-signal co-simulation, Real Number Mod

AI Automation Ethernet Firmware PCIe +5 skills
160K – 200K $
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Astera Labs
13 views 19 hours ago

Senior Design Verification Engineer

Open 30d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Astera Labs is hiring a Senior Design Verification Engineer in San Jose to verify next-generation connectivity silicon (PCIe Gen 6/7, UALink, UCI) for rack-scale AI infrastructure. Day to day: building UVM/SystemVerilog testbenches, defining coverage models, debugging simulations, and driving coverage closure with RTL and post-silicon teams.

AI Automation Ethernet Firmware PCIe +6 skills
149K – 165K $
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Astera Labs
7 views 19 hours ago

Principal Physical Design Engineer

Open 17d APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Astera Labs is hiring a Principal Physical Design Engineer in Ahmedabad to own complex SoC/silicon backend design from synthesis through GDSII (place-and-route, CTS, STA, physical verification) at 16nm-and-below nodes, using Cadence/Synopsys flows for its AI connectivity chips. Requires 8+ years' experience plus Verilog/SystemVerilog, DFT, and Python/Perl scripting.

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Astera Labs
6 views 19 hours ago

Principal Physical Design Engineer

Open 15d APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Physical design engineer at Astera Labs implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes: floorplanning, placement, CTS, routing, EM/IR and congestion analysis, ECOs, and DRC/LVS/ERC signoff using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills
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Astera Labs
6 views 19 hours ago

Teach Lead Physical Design Engineer

Open 15d APACLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Lead physical design engineer at Astera Labs in Singapore implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes. Day-to-day covers floorplanning, placement, CTS, routing, EM/IR and signoff (DRC/LVS/ERC) using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills
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