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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Lead the definition and RTL implementation of datacenter-class System IP (MMUs, interconnects, memory controllers, peripherals) for Tenstorrent's next-generation AI/RISC-V SoCs. Hands-on technical leadership in Verilog/SystemVerilog with protocols like AXI, PCIe, DDR, and USB, based hybrid in Bangalore.
Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller and support multi-chip integration. The role involves designing test plans, building verification infrastructure, and debugging hardware/software flows using SystemVerilog, UVM, and C/C++.
Senior pre-silicon verification engineer building end-to-end test flows for AI accelerator silicon, from IP to SoC and emulation, using UVM and AI-assisted tooling.
Eocene Environmental Group is hiring a full-time, remote Environmental Project Manager (US/Canada) to lead utility, water, solar, and telecom development projects — managing client relationships, budgets, schedules, and multidisciplinary environmental teams. Requires a relevant degree and 5+ years in environmental consulting; pays $90k-$130k.
Designs and verifies custom silicon for autonomous vehicles, using UVM/SystemVerilog to validate hardware functionality and performance in a hybrid work environment.
Senior FPGA Verification Engineer develops and maintains advanced UVM/SystemVerilog test benches for quantum control systems, ensuring reliability and performance through constrained-random testing, coverage analysis, and CI pipelines.
Dein Team Du willst nicht nur Leads sammeln, sondern verstehst, dass hinter jeder Aussteller- und Partneranfrage ein Unternehmen steckt, das zur richtigen Zeit den richtigen Impuls braucht? Du denkst in Funnels statt…
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't…
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Wir suchen ein neues Mitglied (m/w/d) für unser Content Team. Was wir machen? Wir sind eine der führenden Agenturen im Bereich TikTok & Meta in Deutschland und die kreativen Köpfe hinter der Werbung von bekannten…
Directs SoC design verification strategy, methodology, and distributed teams at Ayar Labs in Bengaluru (on-site), hands-on with SystemVerilog/UVM verification of complex SoCs integrating ARM/RISC-V subsystems, coherent interconnects, memory, and high-speed I/O (PCIe, CXL, Ethernet, UCIe, SerDes) for AI, networking, and data-center applications.
Ayar Labs is hiring a Principal Design Verification Engineer in Bengaluru to lead verification strategy for its next-generation silicon photonic (co-packaged optics) chip. The role involves architecting scalable UVM testbenches, setting verification methodology, debugging complex hardware issues, automating regressions, and mentoring engineers using SystemVerilog/UVM, protocol knowledge (PCIe, AMB
Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.
JOB TITLE: Executive Assistant to the President & CEO REPORTS TO: President & CEO EXPECTED SALARY RANGE: $ $70,000 – 85,000; plus the UVM Foundation’s progressive benefits package which includes: a…
Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation…
Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…
Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless…
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