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Designs and verifies digital and mixed-signal SoCs using SystemVerilog/UVM, C, and assembly; builds UVM testbenches, assertions, and coverage models to ensure chip correctness.
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Senior Emulation / Pre-Silicon Validation Engineer (Cadence Palladium) Location: Bengaluru, Karnataka, India Department: Weekday's Client via platform Workplace: on_site Employment Type: full Description 𝗧𝗵𝗶𝘀…
Designs and verifies system-on-chip (SoC) testbenches for AI accelerators, ensuring correctness and performance in hardware development workflows.
Designs and implements System-on-Chip verification environments and testbenches for AI hardware, using industry-standard methodologies and tools.
Pre-Silicon Validation Engineer Location: India Department: Weekday's Client via platform Workplace: remote Employment Type: full Description This role is for one of the Weekday's clients Min Experience: 6+…
Design Verification Engineer at Weekday AI: builds and validates AI hardware designs to ensure correctness and performance before tape-out.
Design verification engineer building and validating custom TPU silicon for Google’s AI/ML workloads using SystemVerilog and UVM.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route market data efficiently.
Leads verification of next-gen RISC-V processor IP using SystemVerilog/UVM, ensuring functional correctness and silicon readiness for GlobalFoundries' semiconductor products.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Systems Verification -…
Design and implement FPGA-based digital logic using VHDL/Verilog, verify designs, and optimize for performance and power in a high-tech hardware environment.
Lead the full lifecycle of NVIDIA’s next-gen switch ASICs, coordinating RTL design, verification, physical design, and post-silicon bring-up with cross-functional teams.
Lead a team verifying low-power features in complex SoC designs using UPF/CPF methodologies, building SystemVerilog/UVM testbenches and driving coverage closure.
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and chip-level functionality across global projects.
Designs and implements verification environments for advanced hardware blocks using SystemVerilog/UVM, driving test plans and low-power checks to ensure silicon-quality devices.
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Designs and implements firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.
Als zentrale Instanz in unserem Partner-Management-Team bist du die Schnittstelle zwischen unseren exklusiven Digital-Plattformen (inklusive unserer Kundenplattformen wie Payback oder Miles&More) und unseren…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
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