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Design and develop firmware for microcontroller-based systems (8051, Arduino, STM32) and create simple custom PCBs from schematic to layout.
Design and maintain FPGA prototyping platforms (HAPS/Xilinx) and write C/C++ firmware tests for SoC verification, debugging silicon bring-up issues in the lab.
Test Architect / Principal Test Engineer — Optical Engine Location: Palo Alto, CA Department: Packaging & Ops Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in…
Design and maintain embedded firmware in C for ARM Cortex-M devices, debug hardware/software issues, and build Python host tools for device control and automation.
Location: This position will be onsite at our corporate offices in Allen, Texas (Dallas-Fort Worth area). Full-time W-2 ONSITE opportunity (not remote)! Work Eligibility: Candidates must be legally authorized to work…
Perform penetration tests on hardware, software, cloud, mobile, and OT solutions to find and exploit vulnerabilities before product release, using tools like Metasploit and custom LLM-assisted tools.
Разрабатывает ядро Linux-подобной ОС и системное ПО для сетевой безопасности, пишет низкоуровневый код на C, тестирует и отлаживает решения.
Designs and optimizes NAND Flash-based storage systems for AI infrastructure, focusing on thermal and power management with firmware integration and validation.
Define and implement firmware for next-gen AI cluster switches, bridging ASIC silicon with cluster orchestration software to maximize bandwidth, minimize latency, and ensure reliability across thousands of AI accelerators.
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
Designs and executes hardware security assessments for Arm’s SoC platforms, identifying silicon-level vulnerabilities and collaborating with teams to implement mitigations.
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Leads firmware architecture and development for embedded optical/photonic systems, owning end-to-end workflows from requirements to production, with expertise in RTOS, bare-metal C/C++, and hardware-firmware integration for high-reliability products.
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Architect and develop firmware simulators for SSD controller SoCs, including register-level IP models and NAND flash models, using C/C++ and SystemC, while mentoring and training teams on simulator usage.
Senior Embedded Software Engineer for robotics developing C++ firmware on ARM Cortex-M microcontrollers to control motors, actuators, and sensors for lab automation systems, ensuring precision, reliability, and integration across hardware modules via CAN/Ethernet.
Design and implement FPGA firmware for next-gen radar and sensing systems, integrating with software and hardware for defense and commercial applications.
Design and implement FPGA-based digital signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused product company.
Design and implement FPGA-based signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused R&D environment.
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