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Principal Product Application Engineer at Astera Labs designs and troubleshoots PCIe connectivity solutions for AI infrastructure, working with hyperscalers and OEMs to deploy high-speed retimers and influence product direction.
Principal Product Manager at Astera Labs in San Jose defines and drives the Smart Cable Modules product line, collaborating with hyperscalers to deliver high-bandwidth connectivity solutions for AI and cloud infrastructure using PCIe, Ethernet, CXL, and related technologies.
Principal Silicon Validation Engineer at Astera Labs in San Jose, CA designs and executes electrical tests to validate AI connectivity hardware, using PCIe, Ethernet, and CXL technologies.
Principal Silicon Validation Engineer designs and runs electrical tests to verify high-speed connectivity chips (PCIe, PAM4 Ethernet) meet strict performance margins for AI infrastructure products.
Leads supplier quality engineering for AI connectivity hardware, partnering with global manufacturers to ensure product quality and reliability using advanced analytics and AI/ML tools.
Quality Engineer driving root-cause analysis of failures across semiconductor circuit, package, firmware, and protocol layers for PCIe and Ethernet connectivity solutions. Uses advanced lab instrumentation (BERT, oscilloscopes, VNAs, TDR) to debug high-speed SERDES and collaborates cross-functionally to ensure product reliability for AI infrastructure hardware.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Senior software engineer building diagnostics and manufacturing tools for high-speed datacenter hardware, using Python and embedded/Linux systems to validate and bring up AI connectivity boards.
Leads a team validating cutting-edge AI connectivity silicon and systems for Astera Labs, ensuring performance and reliability for hyperscale AI deployments using CXL, PCIe, Ethernet, and related protocols.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Leads the product strategy for a unified management suite that orchestrates software, firmware, and silicon across Astera Labs' AI connectivity products, focusing on PCIe, CXL, and Ethernet technologies.
Senior engineer validates high-speed connectivity chips and boards for AI data centers, designing automated tests for CXL, PCIe, and Ethernet compliance and performance.
Senior engineer validates AI connectivity SoCs on emulation platforms, debugging high-speed interfaces like PCIe and Ethernet before silicon tape-out.
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Designs and implements advanced semiconductor packages for high-performance AI connectivity chips, collaborating with teams to optimize electrical, thermal, and mechanical performance from concept to production.
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