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Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Designs and runs tests to validate high-speed semiconductor chips (CXL, PCIe, Ethernet) for AI infrastructure, ensuring reliability and performance in server/storage systems.
Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.
Lead embedded firmware development for analog and Ethernet connectivity devices, writing C/C++ code for calibration, link management, and hardware bring-up in a fast-moving AI infrastructure startup.
The Firmware Engineer Tech Lead will architect and develop firmware for SoC and system products, focusing on connectivity solutions for AI infrastructure. The role involves implementing key product features, collaborating with hardware teams, and engaging directly with customers.
Senior Sourcing Specialist in Taipei manages procurement, supplier relations, and purchasing for Astera Labs' Asia operations, including lab equipment, facilities, and office needs across multiple cities.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads a team to design and tape out advanced multi-die switching chips for AI infrastructure using UCIe, UALink, and PCIe Gen 6/7 in 7nm or smaller process nodes.
Principal Analog Design Engineer at Astera Labs designs high-performance analog and mixed-signal circuits for AI connectivity hardware in San Jose, CA.
Senior Program Manager, HR Operations at Astera Labs manages global immigration programs and HR operations for a high-growth AI infrastructure company, ensuring compliance and scalable processes.
Leads post-silicon validation and bring-up of high-speed SerDes (NRZ/PAM4) hardware, debugging mixed-signal issues (jitter, equalization, PLL/CDR) and automating test frameworks with Python/C++ to validate AI infrastructure connectivity chips for hyperscalers.
Lead Astera Labs' offensive security strategy, conducting red teaming and penetration testing across silicon, firmware, systems, and cloud to proactively find and remediate vulnerabilities before adversaries exploit them.
Define and implement end-to-end security architecture for AI infrastructure hardware, firmware, and cloud services at a semiconductor company powering large-scale AI clusters.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Designs and implements RTL for high-speed interconnect silicon (PCIe, CXL, Ethernet) that powers AI infrastructure, shepherding blocks from spec to tapeout.
Leads end-to-end physical design of high-performance AI infrastructure SoCs, owning floorplanning, timing, power, and signoff for advanced process nodes (7nm+) while mentoring engineers and collaborating with RTL, DFT, and analog teams.
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