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Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
1 SPS-Programmierer Smart Home (f/m/x) Wir bauen nicht wie andere - wir bauen voraus.Denn moderne Häuser brauchen mehr als gute Technik. Sie brauchen intelligente Systeme, die Komfort, Energieeffizienz und…
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Designs and develops ASICs for optical transceivers in next-gen optical modems, focusing on HDL-based digital circuit implementation, synthesis, timing analysis, and RTL verification.
Principal-level verification lead for next-generation semiconductor memory interface products (DDR6 data buffers) at Renesas in San Jose. Day to day: architecting SystemVerilog/UVM testbenches, defining verification strategy, driving coverage closure, and mentoring verification engineers.
AMD is hiring a Design Verification Engineer in Iasi, Romania to join the Infinity (Data) Fabric IP team, supporting pre-silicon verification of modern microprocessor IP. Day to day: writing and running directed and constrained-random tests, debugging simulations with VCS/Verdi, maintaining test plans and docs, and automating workflows with Python/Perl.
Seasoned DSP Hardware Design expert with 7+ years of experience in taking complex digital signal processing solutions from RTL development to silicon. Strong expertise in Verilog RTL design, fixed-point arithmetic,…
Lead design verification engineer at Google owning functional verification strategy and methodology for TPU SoCs — acting as the main contact for IP/SoC verification and coordinating architecture, design, silicon validation, and software teams toward bug-free silicon. Core techniques include UVM, formal, GLS, UPF power simulation, and C-based testing.
Senior Digital Design Engineer on Murata Finland's ASIC Design Team in Vantaa, taking digital ASIC designs from early concept through mass production for safety-critical gyroscope and accelerometer sensors. Core work is Verilog/VHDL RTL design, design verification, and understanding the RTL-to-GDSII flow, in a hybrid work model.
Seit 1948 ist die DENK PHARMA GmbH & Co. KG als Familienunternehmen in mehr als 80 Ländern tätig. Unter unserem Slogan „Quality for your Health – Made in Germany“ schaffen wir für alle Kunden mit unseren Produkten…
An intern role verifying digital designs and SoCs (CPUs, DSPs, security hardware) for IoT chips at Ambiq. Day to day: building UVM/SystemVerilog testbenches, developing test plans and coverage metrics, automating randomized testing, and debugging issues with design teams.
Design verification engineer to validate custom silicon for AI hardware, writing test plans and debugging RTL in UVM/C++ for complex SoCs.
befristet auf 2 Jahre (mit Option auf Verlängerung/Entfristung) | 75% - 100% QPLIX wächst. Und mit uns die Zahl der Menschen, die wir davon überzeugen wollen, Teil von etwas Besonderem zu sein. Wir sind ein innovatives…
Responsibilities: Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and…
The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
Position Overview: As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in…
Description: You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You…
Responsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and…
As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying…
We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and…
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