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Lead the roadmap for AMD’s FPGA/SoC simulation tools (UVM, SystemVerilog, HDL), RTL encryption, and deployment workflows, shaping verification methodologies and influencing industry standards.
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Design and implement verification environments for AMD’s Network-on-Chip IPs and SoCs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness.
Design and verify custom silicon for Google’s devices, building UVM testbenches and formal verification flows to ensure ASICs meet performance and reliability targets for AI and image-processing hardware.
Principal Engineer leads verification strategy for next-gen UA Link Switch SoCs, using UVM/SystemVerilog to ensure first-silicon success for high-speed interconnect and memory subsystems.
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Principal Firmware Engineer in Luton designing and auto-generating firmware for complex digital systems using MATLAB, Simulink, Verilog, and FPGA tools.
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating full-chip verification with SystemVerilog/UVM, Python, C/C++, and AI tools.
Design and verify ASIC blocks and full chips for Cisco’s networking hardware using SystemVerilog/UVM, then bring up silicon and analyze performance.
Design and verify satellite modem IP and subsystems for Amazon’s LEO internet network, using UVM, SystemC, and DPI-C to test against Matlab/C models.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
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Design and verify ASIC/SoC hardware using UVM, SystemVerilog, and Synopsys tools to catch silicon-critical bugs before tape-out.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Staff Design Verification Engineer to verify high-performance CPU cores (frontend, midcore, load-store, prefetch) using SystemVerilog/UVM, debug microarchitectural issues, and drive coverage closure for next-gen RISC-V processors.
Own verification of high-performance CPU cores using SystemVerilog/UVM, writing test plans, assertions, and coverage to catch corner-case bugs in out-of-order pipelines.
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