Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
Develops firmware and microcontroller subsystems for AI connectivity hardware using C/C++, Python, and RTOS, debugging with JTAG and lab tools in Vancouver.
Intern designs and maintains tools to integrate, debug, and deploy Astera Labs' AI connectivity hardware and software, working with PCIe, Ethernet, CXL, and related technologies.
The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.
Electrical engineer on Apple's iPad System EE team in Shenzhen, owning logic board and flex circuit design, power distribution, bringup/debug/validation, and factory NPI support from concept to ship.
Principal firmware engineer designing and validating server SoC firmware for Azure’s next-gen hardware, enabling silicon bring-up, debug, and cross-team collaboration.
Role Overview We are seeking a highly experienced Staff Verification Engineer to lead the design verification of next-generation high-speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in…
Embedded Systems & Sensor Software Engineer responsible for developing software architectures for airborne LiDAR and remote sensing platforms, focusing on embedded systems, sensor integration, and reliability for geospatial services company Woolpert.
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
The Senior Digital Design Engineer will design and implement FPGA architectures and DSP algorithms for real-time defense applications. The role involves high-speed interface integration, system-level architecture decisions, and close collaboration with hardware and software teams.
Designs next-gen Adaptive/Embedded SoCs for AI, data center, automotive, and aerospace, optimizing low-power architectures with processors, accelerators, and I/O subsystems across chiplet/monolithic/3D form factors.
Job Description Location: Hong Kong — on-site (factory floor, test lab and manufacturing sites; this is not a remote or desk-based role) Start date: ASAP Languages: Fluent English and fluent Mandarin are both mandatory…
This role involves leading a software engineering team focused on developing test frameworks and content for TPU silicon validation. The manager will oversee technical roadmaps, guide system design, and collaborate with hardware teams to ensure the functionality and performance of cutting-edge AI chips.
We are looking for an Embedded Software Engineer to join a defense tech project on a full-time contract basis. The project involves building low-level software for embedded platforms with on-device AI acceleration.…
We couldn't check your fit for this role — add a CV to your profile to see it next time.