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Design and run verification tests for CPU cache and memory subsystems, focusing on coherency, ordering, and corner-case bugs using SystemVerilog/UVM.
Staff engineer verifying CPU cache and memory-subsystem designs using SystemVerilog/UVM, focusing on cache coherency, ordering, and corner-case bugs.
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Designs and runs SystemVerilog/UVM testbenches to verify Arm-based CPUs, PCIe, DDR, and SoC subsystems, writing C/C++/Assembly tests and debugging RTL issues.
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Designs and verifies mixed-signal SoCs for wireless systems, building analog/system models and testbenches in SystemVerilog/VerilogAMS to validate functionality before tape-out.
Design and implement high-performance CPU frontend features for RISC-V cores using Chisel/Verilog, focusing on instruction fetch, decode, and branch prediction while collaborating with verification and physical design teams.
Leads hardware verification for AI-generated chip designs, ensuring rigorous validation of custom ASICs at tapeout stage using SystemVerilog, UVM, and Python, while collaborating with AI/ML and architecture teams to refine verification strategies and methodologies.
Lead AMD’s pre-silicon verification strategy, defining next-gen architectures and methodologies to ensure first-pass silicon success for complex SoC designs using advanced EDA tools and ML/AI innovations.
Designs and verifies peripheral IP blocks (PCIe, CXL, USB, Ethernet) using SystemVerilog/UVM, coverage-driven random testing, and C-based reference models.
Designs and verifies ASIC IP for Qualcomm’s Snapdragon DSP/NPU, using UVM and SystemVerilog to accelerate AI and video workloads in connected devices.
Design Verification Engineer builds and runs ASIC/SoC verification environments using SystemVerilog and UVM to ensure chip designs meet specifications.
Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.
Designs and verifies hardware infrastructure, focusing on DDR subsystem verification for Qualcomm’s next-gen products. Uses UVM, SystemVerilog, and debug tools to create test plans, integrate verification IP, and ensure high-quality verification of digital/analog/RF systems.
Design verification engineer building and debugging SystemVerilog/UVM testbenches for custom AI silicon IP and SoCs, ensuring functionally correct RTL before tape-out.
Designs and implements RTL logic for Intel’s IP blocks, focusing on secure memory access, error handling, and debug/telemetry features to ensure high-performance SoC reliability.
Lead AI-driven frontend verification products (RCA and Coverage) for semiconductor design, defining roadmaps, validating customer value, and driving sales from wedge use cases to full-SoC deployments.
Design and verify RTL hardware designs and SystemVerilog/UVM testbenches to train AI agents that automate chip design workflows.
Applications Engineer at ChipAgents guides enterprise customers through AI-driven chip design and verification workflows, integrating tools like Synopsys VCS and Cadence Xcelium to accelerate RTL development and verification.
Design and verify FPGAs for spacecraft test infrastructure, bridging hardware interfaces and enabling real-time functions like packet timestamping and command scheduling.
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