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OPENING DATE: August 27, 2026 CLOSING DATE: September 11, 2026 SERIES/GRADE: 0855/15 TYPE OF POSITION: Trust Indefinite (Non-Federal) DIVISION: Central Engineering LOCATION: Cambridge, MA AREA OF CONSIDERATION: This…
Design and implement FPGA/ASIC applications using OCaml and Hardcaml (an OCaml RTL library) for RTL design and testing, with some Verilog and C work, at a quantitative trading firm.
Interns collaborate with full-time engineers on FPGA/ASIC hardware projects using OCaml and Hardcaml, from design to validation, with mentorship and exposure to Jane Street’s internal tools.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.
Senior Technical Staff Engineer responsible for developing Signal and Power Integrity methodologies for high-speed FPGA products, running pre- and post-layout SIPI simulations, optimizing PDN and SerDes transceivers, and mentoring a global cross-functional team at Microchip in San Jose.
Please follow the link to apply selecting "Microchip Recruiter" as your source: https://wd5.myworkdaysite.com/en-US/recruiting/microchiphr/External/job/Manager---Product-Marketing_R3664-26 Job Description:…
Design and optimize FPGA fabric architecture—interconnect, routing, logic elements, memory blocks, and clocking—at Microchip's FPGA Business Unit, using full-custom mixed-signal design, HDLs (Verilog/VHDL), and scripting on advanced process nodes.
As the RF Software Manager at Impulse, you will lead the team responsible for the software and FPGA firmware that powers our spacecraft communication and GPS/GNSS receiver systems. You will own the development and…
Design and optimise FPGA-based systems for low-latency, high-throughput data processing and custom hardware acceleration in a small hardware engineering team focused on performance-critical infrastructure.
There are over 7 billion people on this planet. And by 2050, there will be 2 billion more... many moving into urban centers at an unprecedented rate. Making sure there is enough food, fiber and infrastructure for our…
Senior FPGA Design Engineer converts ASIC designs to FPGA, writes RTL conversion scripts, debugs hardware/firmware issues, and collaborates with global teams using Verilog/VHDL and FPGA tools.
You'll join a company where your work has visible impact from day one. You'll work directly with world-class engineers, scientists, aerospace experts and entrepreneurs building technologies that have never…
Senior FPGA Engineer designing and optimizing FPGA-based systems for low-latency, high-throughput data processing, working on custom hardware acceleration and high-speed data pipelines.
Salary: £85,000 - 85,000 per year Requirements: Strong FPGA design and development experience VHDL experience Digital signal processing (DSP) experience Experience developing FPGA-based solutions for communications…
Salary: £100,000 - 100,000 per year Requirements: Experience as a Head of Embedded Software, Head of Software, Software Development Manager, or in a similar leadership role Experience in some of the following technical…
Salary: £60,000 - 90,000 per year Requirements: Strong commercial experience developing FPGA solutions using VHDL and/or Verilog. Hands-on experience with FPGA toolchains such as Xilinx Vivado and/or Intel Quartus.…
The Senior FPGA Engineer designs and implements high-assurance cryptographic firmware in VHDL for government and defense applications. The role involves leading architectural decisions, mentoring team members, and ensuring rigorous verification within a specialized security-focused team in Delft.
Develops bare-metal embedded flight software in C for space-based imaging payloads, focusing on real-time servo control and hardware integration. Core technologies include C/C++, Jenkins/CI, and resource-constrained aerospace hardware.
Designs and implements ASIC IPs and system features for Mobileye’s next-gen SoC, focusing on ADAS and autonomous vehicle technologies, including RTL development, verification, synthesis, and timing closure.
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