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Leads digital IC verification for mixed-signal IP (DACs, ADCs, PLLs) in automotive/industrial/medical products, designing SystemVerilog/UVM environments, debugging RTL, and improving verification methodologies.
Designs and implements C-based tests for wireless SoC verification and power analysis, collaborating across chip disciplines to ensure functional silicon for Apple products.
Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities:…
Build and maintain UVM/SystemVerilog testbenches to verify PCIe and memory-subsystem RTL, collaborating with architects and post-silicon teams to ensure robust, high-performance designs.
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Build AI-powered tools to automate and enhance semiconductor verification workflows, using Python, LLMs, and cloud DevOps for faster, smarter hardware development.
Designs prints, patterns, and illustrations for private-label products, creates moodboards, and supports production specs using Adobe CC and CAD tools in a hybrid role.
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An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Principal Engineer leading pre-silicon verification of complex digital SoCs, AI/ML accelerators, and high-speed peripherals using UVM, formal methods, and emulation for edge computing products.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Lead FPGA design and architecture for defense electronics using VHDL, targeting Xilinx/Altera/Microsemi devices, and verify with constrained-random testing.
Building Name: Porter - Porter Medical Center Location Address: 115 Porter Drive, Middlebury Vermont Regular Department: Porter - Plant Operations Full Time Standard Hours: 40 Biweekly Scheduled Hours: Shift: Day…
Designs and integrates RTL blocks into SoCs, runs linting, CDC/RDC checks, synthesis, and gate-level simulations using tools like NCSim and VCS.
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Senior Hardware Design Engineer Department: US Jobs Employment Type: Permanent Location: West Coast, United States, Hybrid We are looking for multiple Senior Design Engineers who will work on revolutionary technology…
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Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.
Lead a team building and verifying hardware IP and SoCs for high-speed interfaces like PCIe and Ethernet using C/C++ and UVM, driving Cadence’s electronic design automation tools.
Designs and verifies high-speed protocol IP (e.g., PCIe, Ethernet) for emulation and prototyping tools using Verilog, UVM, and FPGA flows.
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