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Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.
Design verification engineer building and running testbenches for high-speed storage IP (HDD/SSD) using SystemVerilog/UVM and collaborating with SoC teams to debug complex digital designs.
Architects and implements pre-silicon verification strategies using UVM or formal methods, builds testbenches, and integrates block-level tests into chip-level environments for Intel hardware designs.
Validates mixed-signal hardware designs before fabrication, using SystemVerilog and UVM to ensure performance, power, and area goals are met.
- Bachelor's degree or above in computer science, electrical engineering, or related field - - 3+ years of hands-on post-silicon validation or system validation engineering experience - - Strong programming skills…
- Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Experience developing products for volume production - Experience low power design techniques - Master's degree…
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
Lead ASIC verification for Google Cloud hardware, owning outcomes, decisions, and stakeholder alignment using SystemVerilog and UVM.
Senior Principal FPGA Verification Engineer - $30K Sign On Bonus Location: Westminster, Colorado, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Minimum $30,000 Sign On…
InfoTip digitalisiert seit über 25 Jahren Service-, Sales- und CRM-Prozesse für Kunden vom Mittelstand bis zu internationalen Marken. Salesforce ist einer der wichtigsten Wachstumstreiber bei InfoTip. Deshalb suchen…
SMMU Senior Lead Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
DSP / NPU Staff Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
LPASS Design Verification Sr Lead Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Design verification engineer leading pre-silicon verification for complex SoCs, using UVM, SystemVerilog, and formal methods to ensure correctness of AI/ML accelerators, processors, and interconnects.
Senior engineer verifying FPGA-based designs for NVIDIA’s Holoscan edge-compute platform, using SystemVerilog/UVM and collaborating with architecture teams to validate real-time AI and connectivity features.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Designs and implements secure, high-performance IP blocks for Intel’s Unified Chassis, focusing on AXI/APB bridges, ECC/parity schemes, and RAS/debug telemetry for SoC reliability.
Verifies CPU logic before manufacturing by writing test benches in SystemVerilog/UVM, running simulations, debugging failures, and collaborating with architects to meet specs.
Design and verify ASIC/SoC hardware in Verilog/SystemVerilog, then evaluate and improve how AI models understand chip engineering tasks.
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