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Design and validate high-performance SSD hardware, lead interoperability testing, and mentor junior engineers using PCIe, DDR, NAND, and scripting tools.
Architect and lead the software stack for Google's AI and HPC accelerator platforms (GPUs, TPUs), focusing on distributed systems, Linux OS internals, networking, and hardware bus integration (PCIe) for massive-scale data center deployment.
Architect Linux-based RF software for autonomous systems, building high-performance C++ apps and kernel modules to enable reliable communications and sensing for drones and unmanned vehicles.
Designs and prototypes secure hardware devices, from concept to mass production, while ensuring manufacturability, security, and reliability for authentication products.
Develop embedded firmware and low-level tools for SoC validation, working closely with hardware teams to enable silicon bring-up and debugging at scale.
Senior software engineer on AMD's Data Center Solutions team in Hyderabad, doing firmware, Linux driver, and embedded application development for AMD storage and networking IPs on AMD's All Programmable Platform.
This role involves managing a Silicon Engineering group at AMD, focusing on FPGA design and high-speed protocols like PCIe, Ethernet, and USB. The manager will lead a high-performance team, nurture talent, and collaborate with cross-functional partners to deliver next-generation computing technologies.
This Firmware Engineer role involves developing low-level software for advanced AI semiconductor systems using C/C++, RTOS, and Embedded Linux. The position requires deep knowledge of SoC architecture and hardware-software interfaces to support complex system development.
Designs fault-tolerant software and firmware for Google’s server fleet, bridging hardware/software boundaries to detect, diagnose, and mitigate failures while optimizing reliability and cost. Core tech: C++, distributed systems, hardware telemetry, and RAS frameworks.
Сбер начинает работу над квантовым компьютером и аналоговыми вычислителями. Мы предлагаем вам присоединиться к команде Центра Квантовых Технологий Сбера, чтобы решать самые интересные задачи на переднем крае науки и…
The SSD Tester Development Engineer will design and maintain next-generation NVMe SSD testing equipment, focusing on system architecture, PCIe high-speed circuits, microcontroller firmware, and FPGA development.
Silicon Quantum Computing (SQC) is at the forefront of global efforts to build the world’s first commercial-scale quantum computer, while delivering quantum-enhanced AI and simulation products to customers today.…
This role involves designing and maintaining verification plans and SystemVerilog/UVM testbenches for ARM's scalable coherent mesh network interconnects. Engineers will collaborate with architects to debug functional failures and improve verification methodologies for high-performance compute and AI applications.
Develops low-level system software for next-gen cloud routing products, focusing on hardware interfaces like optics, PCIe, and Ethernet, using C/C++ and Linux fundamentals in a distributed systems environment.
Designs and layouts complex printed circuit boards for networking devices, collaborating with hardware and mechanical teams to drive prototyping and mass production.
Develops and optimizes test programs for SSD/UFS controllers, automates testing via scripting, and collaborates with engineering teams to improve product yields and efficiency using mixed-signal test tools and semiconductor manufacturing knowledge.
The Senior Staff QA Engineer will design and maintain automation frameworks and validate firmware for PCIe, CXL, and memory controller products. The role involves using C/C++, Python, and CI/CD pipelines to ensure high-quality releases for semiconductor data infrastructure.
The Principal Software Engineer leads a team in validating and productizing infrastructure system solutions for Arm's Neoverse platforms. The role involves hands-on technical leadership, developing validation plans, and improving CI/CD infrastructure for complex SoC environments.
The Principal Systems Development Engineer leads the hardware development lifecycle for networking components like NIC cards, managing electrical activities from design through production. The role involves collaborating with cross-functional teams and ODMs to ensure high-quality integration of PCIe, Ethernet, GPU, and DPU technologies.
This role involves developing and sustaining FPGA firmware and embedded software for flow cytometry instruments, focusing on high-throughput data acquisition and hardware control. The engineer will work with Verilog/SystemVerilog and embedded systems to ensure reliable instrument performance in a laboratory environment.
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