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As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and…
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: .We are seeking a visionary and technically accomplished Director, Verification CAD…
My client is a leading organisation in Secure communications and Data at Rest domain! They are expanding their UK team to support multiple Cyber and Information Assurance development projects. The company is seeking an…
Senior FPGA / ASIC Design Engineers - 5G & Satellite Technology Spectrum IT Recruitment is working with a cutting-edge technology business in Southampton that is expanding its engineering team and looking for…
Job DescriptionJob Description Job Title: Senior FPGA Engineer Department: Engineering Reports To: Functional Team Lead / Program Manager FLSA Status: Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are…
Hardware Developer - Z, EDA, IBM Corporation, Austin, TX (Up to 40% telecommuting permitted): Customize Cadence graphical user interfaces (GUIs) based on user requirements using the Cadence SKILL programming language.…
Building Name: PMC - Helen Porter Nursing Home Location Address: 30 Porter Drive, Middlebury Vermont Regular Department: Porter - HP Memory Care Full Time Standard Hours: 36 Biweekly Scheduled Hours: 72 Shift:…
Gemeinsam lebenswerte Orte schaffen. Als DV Immobilien Gruppe bauen und betreiben wir Business Parks, Shopping Center und Autohöfe für den Eigenbestand. Gemeinsam entwickeln wir innovative Standortkonzepte mit dem Ziel…
In unserer Abteilung IT & Prozesse sorgst Du gemeinsam mit Deinen Kollegen dafür, dass unsere IT-Systeme zuverlässig laufen und unsere Mitarbeiter in Verwaltung, Produktion und Logistik optimal arbeiten können.…
Es freut uns, dass du da bist! Neue Technologien reizen dich, und du möchtest mit deinem Fachwissen smarte Lösungen für die Logistikbranche schaffen? Wir, die proLogistik Group, sind Marktführer für Systemlösungen in…
You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile…
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Principal Digital Design Engineer at Astera Labs in Taipei will architect and implement complex digital blocks for high-performance AI connectivity silicon, owning designs from micro-architecture through silicon bring-up. Core technologies: RTL design, Cadence/Synopsys flows, PCIe/Ethernet/DDR protocols, timing closure, DFT, and UVM verification.
Lead design verification of CXL, PCIe, and Ethernet connectivity IPs and SoCs at Astera Labs — defining verification strategy, building UVM/SystemVerilog environments, driving coverage closure and sign-off, and mentoring engineers to achieve first-pass silicon success. Requires 10+ (Principal) or 15+ (Senior Principal) years of DV experience.
Senior silicon design verification engineer who plans, builds, and runs verification for AMD's graphics processor IP — writing directed and constrained-random tests, debugging RTL/firmware failures, and improving UVM-based verification methodology. Core stack: SystemVerilog/UVM, Verilog, C/C++, and simulation tooling in Linux (and some Windows) environments.
Overview Do you want to be at the forefront of innovating the latest hardware designs to propel Microsoft’s cloud growth? Are you seeking a unique career opportunity that combines technical capabilities, cross-team…
Hands-on verification lead role at a well-funded semiconductor startup building chiplet power delivery technology for AI/advanced computing. Day to day: architect SystemVerilog/UVM verification environments for complex SoC/IP designs, run RTL and gate-level simulation (Xcelium/VCS), drive coverage closure, and mentor verification engineers. Hybrid: 3 days/week onsite in Vancouver, WA or Chandler,
Senior pre-silicon verification engineer building end-to-end test flows for AI accelerator silicon, from IP to SoC and emulation, using UVM and AI-assisted tooling.
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