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Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Info Du denkst UX nicht nur als schönes Interface, sondern als strategischen Hebel für begeisternde Produkterlebnisse, zufriedene Kunden und den Erfolg von Pixum? Wir auch! Als Head of UX bei Pixum stärkst du die…
Silicon Labs is hiring a design modeling engineer in Austin (hybrid) to build functional and performance models and virtual hardware platforms for its low-power wireless IoT connectivity SoCs. The role spans C/C++ modeling, architecture exploration, and application/driver-level software, working alongside hardware and software architects.
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Dein Team Du tüftelst gerne daran, wie Systeme sauber zusammenspielen, und behältst auch bei komplexen Tool-Landschaften den Überblick? Dann bist du bei OMR genau richtig! Als Teil unseres Marketing Teams sorgst du…
Astera Labs is hiring a Senior Digital Design Engineer in San Jose to develop micro-architecture, RTL, synthesis, and IP integration for high-performance network controllers powering rack-scale AI connectivity. The role works with protocols like PCIe, Ethernet, and UALink using Synopsys/Cadence flows, DFT, UVM verification, and silicon bring-up.
Tech Lead for front-end digital design of high-performance switch ASICs powering rack-scale AI infrastructure at Astera Labs. The role owns blocks from microarchitecture through GDS — RTL, synthesis, timing closure, gate-level simulation, DFT, verification, and silicon bring-up — using Synopsys/Cadence flows and protocols like PCIe Gen 6/7, Ethernet, UALink, and UCI.
Astera Labs is hiring a Tech Lead Digital Design Engineer in San Jose to lead micro-architecture and front-end design (RTL, synthesis, IP integration, block-level verification) of high-performance network controllers for its AI connectivity silicon. Core work spans PCIe/Ethernet/UALink protocols, Synopsys/Cadence flows, DFT, and silicon bring-up.
Astera Labs is hiring a Senior Design Verification Engineer in San Jose to verify next-generation connectivity silicon (PCIe Gen 6/7, UALink, UCI) for rack-scale AI infrastructure. Day to day: building UVM/SystemVerilog testbenches, defining coverage models, debugging simulations, and driving coverage closure with RTL and post-silicon teams.
Lead design verification for Astera Labs' next-generation connectivity silicon (PCIe Gen6/7, UALink, UCIe) that powers rack-scale AI infrastructure. Day to day: build UVM/SystemVerilog testbenches, define verification plans and coverage models, debug simulations, drive regression automation, and partner with RTL, firmware, and post-silicon teams through coverage closure and silicon bring-up.
Principal-level design verification tech lead owning functional verification of high-speed SerDes/PHY IP for AI infrastructure connectivity. Day to day: architecting UVM testbenches, driving coverage closure to tape-out, verifying against PCIe Gen 6/7, UALink, UCIe, and Ethernet PHY specs, and mentoring DV engineers. Core stack: SystemVerilog/UVM, analog/mixed-signal co-simulation, Real Number Mod
Astera Labs is hiring a Principal Digital Design Engineer in San Jose to own front-end silicon design of high-performance network controllers/switch ASICs — micro-architecture, RTL, synthesis, IP integration, DFT, and block-level verification, through production and silicon bring-up. Core technologies include PCIe, Ethernet, UALink, Synopsys/Cadence flows, and UVM.
Builds and maintains UVM-based verification environments (SystemVerilog with C/C++ via DPI/PLI) for connectivity silicon used in rack-scale AI infrastructure, writing tests, assertions, and coverage while debugging across simulation, co-simulation, and FPGA emulation alongside RTL designers.
Lead functional verification of PCIe/CXL semiconductor connectivity designs—develop UVM test plans, write assertions and coverage, debug with RTL designers, and build VIP abstraction layers for SoC products.
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP for its AI connectivity semiconductors. Day to day, this person architects UVM/SystemVerilog verification environments, drives coverage closure through tape-out, and verifies PHY behavior against PCIe Gen 6/7, UALink, UCIe, and Ethernet standards, including analog/mixed-signal
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
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