Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
Designs and validates synthesizable RTL for digital IPs and SoC subsystems using Verilog/SystemVerilog, ensuring clean signoff through Lint, CDC, RDC, and synthesis checks.
Own and execute pre-silicon verification for Silicon IP (e.g., UCIe Interoperability) using UVM/System Verilog, debug failures, and guide junior engineers in ASIC/SoC verification flows.
Design and lead analog/mixed-signal ICs for automotive electrification and smart power, owning the full flow from spec to silicon and coaching junior engineers.
Designs and verifies analog/mixed-signal ASICs for automotive electrification and smart-power systems, leading architecture, verification, and product release while coaching junior engineers.
Salary: 47.000 - 87.000 € per year Requirements: Abschluss in Informatik oder verwandten Studiengängen mit Schwerpunkt Softwareentwicklung Mehrjährige Berufserfahrung als Softwarearchitekt sind von Vorteil Sehr gute…
SoC Verification Engineer The SoC Development team at Sandisk is seeking highly motivated SoC Verification Engineers to join our talented team, working on cutting-edge controller development for high-performance SoCs…
Design a radiation-tolerant RISC-V microcontroller ASIC for particle physics detectors using Verilog, fault-tolerant techniques, and CERN’s SOCRATES framework.
Designs high-speed datapath and circuit blocks for 3D NAND flash memory, including page buffers and RTL logic, using Verilog and simulations to meet performance specs.
Design verification engineer building and running SystemVerilog/UVM testbenches to validate DDR5, LPDDR5/6, and DFI memory interfaces for AMD’s server products.
Designs high-speed memory interface chips using Verilog/SystemVerilog, working with RTL, ASIC flows, and post-silicon validation to optimize data speed and security.
Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.
Leads verification strategy for complex IC designs, guiding teams to build test environments, debug RTL, and improve coverage using UVM, SystemVerilog, and RISC-V protocols.
Designs and validates next-gen memory circuits (HBM) using TSV stacking, CMOS, and SPICE simulations to optimize power, speed, and manufacturability for AI/ML workloads.
Design and verify high-bandwidth memory (HBM) digital logic using Verilog/SystemVerilog, collaborating with verification and physical-design teams to ensure robust closure and post-silicon debug.
Working as part of the ASIC Verification and Validation engineering team, you will create and maintain diagnostic, verification, HAL, and platform firmware running on various pre-silicon and post-silicon platforms for…
Design and implement FPGA firmware for surgical robotics using System Verilog, focusing on video processing, motor control, and high-speed comms, then integrate and validate the designs in Intuitive’s robotic systems.
We couldn't check your fit for this role — add a CV to your profile to see it next time.